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Technical Document


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Datasheet 313
Testability
13 Testability
In the MCH, testability for Automated Test Equipment (ATE) board level testing has
been implemented as an XOR chain. An XOR-tree is a chain of XOR gates each with one
input pin connected to it which allows for pad to ball to trace connection testing.
The XOR testing methodology is to boot the part using straps to enter XOR mode (A
description of the boot process follows). Once in XOR mode, all of the pins of an XOR
chain are driven to logic 1. This action will force the output of that XOR chain to either
a 1 if the number of the pins making up the chain is even or a 0 if the number of the
pins making up the chain is odd.
Once a valid output is detected on the XOR chain output, a walking 0 pattern is moved
from one end of the chain to the other. Every time the walking 0 is applied to a pin on
the chain, the output will toggle. If the output does not toggle, there is a disconnect
somewhere between die, package, and board and the system can be considered a
failure.
13.1 XOR Test Mode Initialization
Figure 15. XOR Test Mode Initialization Cycles
PWROK
RSTIN#
STRAP PINS
HCLKP/GCLKP
HCLKN/GCLKN
XOR inputs
XOR output
CL_PWROK
X
CL_RST#
Testability
314 Datasheet
The above figure shows the wave forms to be able to boot the part into XOR mode. The
straps that need to be controlled during this boot process are BSEL[2:0], RSVD (Ball
L18), EXP_SLR, and XORTEST.
On the X38 Express Chipset platforms, all strap values must be driven before PWROK
asserts. BSEL0 must be a 1. BSEL[2:1] need to be defined values, but logic value in
any order will do. XORTEST must be driven to 0.
Not all of the pins will be used in all implementations. Due to the need to minimize test
points and unnecessary routing, the XOR Chain 14 is dynamic depending on the values
of EXP_SLR, and RSVD (Ball L18). See Figure 30 for what parts of XOR Chain 14
become valid XOR inputs depending on the use of EXP_SLR and RSVD (Ball L18).
13.2 XOR Chain Definition
The MCH has 15 XOR chains. The XOR chain outputs are driven out on the following
output pins. During fullwidth testing, XOR chain outputs will be visible on both pins.
Table 30. XOR Chain 14 Functionality
RSVD (Ball L18) EXP_SLR XOR Chain 14
10
EXP_RXP[15:0]
EXP_RXN[15:0]
EXP_TXP[15:0]
EXP_TXN[15:0]
11
EXP_RXP[15:0]
EXP_RXN[15:0]
EXP_TXP[15:0]
EXP_TXN[15:0]
00
EXP_RXP[15:8]
EXP_RXN[15:8]
EXP_TXP[15:8]
EXP_TXN[15:8]
01
EXP_RXP[7:0]
EXP_RXN[7:0]
EXP_TXP[7:0]
EXP_TXN[7:0]
10
EXP_RXP[15:0]
EXP_RXN[15:0]
EXP_TXP[15:0]
EXP_TXN[15:0]
11
EXP_RXP[15:0]
EXP_RXN[15:0]
EXP_TXP[15:0]
EXP_TXN[15:0]
Datasheet 315
Testability
13.3 XOR Chains
This section provides the XOR chains.
Table 31. XOR Chain Outputs
XOR Chain Output Pins Coordinate Location
xor_out0 ALLZTEST M21
xor_out1 XORTEST L22
xor_out2 ICH_SYNCB P16
xor_out3 RSVD N18
xor_out4 RSVD AN12
xor_out5 RSVD AM14
xor_out6 BSEL1 F21
xor_out7 BSEL2 F18
xor_out8 RSVD AN13
xor_out9 RSVD AP12
xor_out10 EXP_SLR K19
xor_out11 RSVD L18
xor_out12 BSEL0 M22
xor_out13 RSVD H21
xor_out14 RSVD G22
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