CAT871, CAT872
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6
SYSTEM DESCRIPTION AND APPLICATIONS INFORMATION
General
CAT871, CAT872 are designed for the manual resetting of
microprocessors and microcontrollers when normal
resetting mechanisms have failed. To prevent accidental
resets, CAT871, CAT872 require both manual reset inputs
be held low for a prescribed period before a reset pulse is
issued to the system processor.
Manual Reset Inputs
MR1 and MR2 are Schmitt trigger CMOS inputs. Both
inputs must go low and stay low for a predetermined period
(t
LOW_DELAY
) to generate a single reset pulse on the output.
MR1 and MR2 operate independently and may be brought
low at any time and in any order. The last input to reach 0 V
starts the delay timer.
MR1 is a standard CMOS input and MR2 is also a CMOS
input with an internal 200 kW pull−up resistor, thus MR2 can
be left floating whereas MR1 must be biased by a pull−up
resistor, powered switch or some other means external to the
IC. (Consult factory for other input biasing options)
Delay Timer
When both MR1 and MR2 go low, an internal timing cycle
is initiated. If any input goes high before the countdown
timer has concluded its cycle, the timer will reset and will
restart from the beginning when MR1 and MR2 return to
being low.
If both manual reset inputs (MR1 and MR2) remain low
after a reset pulse is issued, no second reset pulse will be
issued after that.
Reset Output
CAT871, CAT872 provide an active−low open drain
output to be wire−OR’d with other open drain reset devices.
This output will sink up to 3 mA and as such will not be
loaded down by low value (strong) pull−up resistors. The
reset pulse is typically 2 ms long for CAT871 and 70 ms long
for CAT872 and is issued at the conclusion of the delay
timer’s countdown sequence.
CAT871, CAT872 will not generate a reset pulse at
power−up.
Delay Timer Testing
To aid in−circuit testing of the delay timer, a special test
function has been included in CAT871, CAT872. This test
mode, TOC, allows the delay timer to clock at an accelerated
rate. Upon the conclusion of the countdown a standard width
reset pulse will be issued and the chip will exit test mode.
To initiate TOC, MR1→ 0 V and a fast external CLK
(typically 1 MHz) is applied on MR2, with the falling edge
of the first clock pulse on MR2 delayed with tP from MR1→
0 V. CAT871, CAT872 look for 8 sequential pulses to appear
on MR2 within 35 ms to confirm TOC is desired. After the
rising edge of the 8’th pulse, there will be a delay of 250 ms
typical followed by a standard reset pulse at the reset output.
This delay is independent of the normal timeout delay
setting.
After issuing the reset pulse, CAT871, CAT872 exit TOC
mode and returns to normal operation. If at any time during
TOC both MR1 and MR2 are HIGH, CAT871, CAT872 will
immediately exit TOC mode.
Figure 12. TOC Mode
