ZY7015 15A DC-DC Intelligent POL Data Sheet
3V to 13.2V Input
• 0.5V to 5.5V Output
If the falling slew rate control is not utilized, the turn-
off delay only determines an interval from the
application of the Turn-Off command until both high
side and low side switches are turned off. In this
case, the output voltage ramp-down process is
determined by load parameters.
8.2.3 Rising and Falling Slew Rates
The output voltage tracking is accomplished by
programming the rising and falling slew rates of the
output voltage. To achieve programmed slew rates,
the output voltage is being changed in 12.5mV steps
where duration of each step determines the slew
rate. For example, ramping up a 1.0V output with a
slew rate of 0.5V/ms will require 80 steps duration of
25µs each.
Duration of each voltage step is calculated by
dividing the master clock frequency generated by the
DPM. Since all POLs in the system are
synchronized to the master clock, the matching of
voltage slew rates of different outputs is very
accurate as it can be seen in Figure 11 and Figure
16.
During the turn on process, a POL not only delivers
current required by the load (I
LOAD
), but also charges
the load capacitance. The charging current can be
determined from the equation below:
dt
dV
CI
R
LOADCHG
×=
Where, C
LOAD
is load capacitance, dV
R
/dt is rising
voltage slew rate, and I
CHG
is charging current.
When selecting the rising slew rate, a user needs to
ensure that
OCPCHGLOAD
III <+
Where I
OCP
is the overcurrent protection threshold of
the ZY7015. If the condition is not met, then the
overcurrent protection will be triggered during the
turn-on process. To avoid this, dV
R
/dt and the
overcurrent protection threshold should be
programmed to meet the condition above.
Figure 36. Tracking Configuration Register TC
8.3 Protections
ZY7015 Series converters have a comprehensive set
of programmable protections. The set includes the
output over- and undervoltage protections,
overcurrent protection, overtemperature protection,
tracking protection, overtemperature warning, and
Power Good signal. Status of protections is stored in
the ST register shown in Figure 37.
Figure 37. Protection Status Register ST
Thresholds of overcurrent, over- and undervoltage
protections, and Power Good limits can be
programmed in the GUI Output Configuration
window or directly via the I
2
C bus by writing into the
CLS and PC2 registers shown in Figure 38 and
Figure 39.
--- R2 R1 R0 F2 F1 F0
Bit 7 Bit 0
R = Readable bit
W=Writable bit
U = Unimplemented bit,
read as ‘0’
-n = Value at POR reset
UR/W-0R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
R/W-1
Bit 7
Unimplemented
, read as ‘0’
Bit 6:4 R[2:0]: Value of Vo rising slope
0: corresponds to 0.1V/ms (default)
1: corresponds to 0.2V/ms
2: corresponds to 0.5V/ms
3: corresponds to 1.0V/ms
4: corresponds to 2.0V/ms
5: corresponds to 5.0V/ms
6: corresponds to 8.3V/ms
7: corresponds to 8.3V/ms
Bit 3 SC, Slew rate control at turn-of
0: Slew rate control is disabled
1: Slew rate control is enabled
Bit 2:0 F[2:0]: Value of Vo falling slope
0: corresponds to -0.1V/ms (default)
1: corresponds to -0.2V/ms
2: corresponds to -0.5V/ms
3: corresponds to -1.0V/ms
4: corresponds to -2.0V/ms
5: corresponds to -5.0V/ms
6: corresponds to –8.3V/ms
7: corresponds to –8.3V/ms
SC
TP PG TR OT UV OV PV
Bit 7 Bit 0
R = Readable bit
W=Writable bit
U = Unimplemented bit,
read as ‘0’
-n =Value at POR reset
R-1 R-0 R-1 R-1
R-1 R-1 R-1
R-1
Bit 7 TP: Temperature Warning
Bit 6 PG: Power Good Warning
Bit 5 TR: Tracking Fault
Bit 4 OT: Overtemperature Fault
Bit 3
OC
: Overcurrent Fault
Bit 2
UV
: Undervoltage Fault
Bit 1 OV: Overvoltage Error
Bit 0
PV
: Phase Voltage Erro
Note:
- An activated warning/fault/error is encoded as ‘0’
OC
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