DESCRIPTION
■ 5V and 3.3V power supplies required
■ Also, supports LVPECL-to-PECL translation
■ 500ps propagation delays
■ Fully differential design
■ Differential line receiver capability
■ Application note
■ Available in 20-pin SOIC package
The SY100EL92 is a triple LVPECL-to-PECL or PECL-
to-LVPECL translator. The device receives standard PECL
signals and translates them to differential LVPECL output
signals (or vice versa). SY100EL92 can also be used as a
differential line receiver for PECL-to-PECL or LVPECL-to-
LVPECL signals. However, please note that for the latter
we will need two different power supplies. Please refer to
Function Table for more details.
VBB outputs are provided for interfacing single ended
input signals. If a single ended input is to be used, the VBB
output should be connected to the D input and the active
signal will drive the D input. When used, the VBB should be
bypassed to VCC via a 0.01µF capacitor. The VBB is
designed to act as a switching reference for the SY100EL92
under single ended input conditions. As a result, the pin
can only source/sink 0.5mA of current.
To accomplish the PECL-to-LVPECL level translation,
the SY100EL92 requires three power rails. The VCC and
VCC_VBB supply is to be connected to the standard PECL
supply, the 3.3V supply is to be connected to the VCCO
supply, and GND is connected to the system ground plane.
Both the VCC and VCCO should be bypassed to ground with
a 0.01µF capacitor.
To accomplish the LVPECL-to-PECL level translation,
the SY100EL92 requires three power rails as well. The 5.0V
supply is connected to the VCC and VCCO pins, 3.3V supply
is connected to the VCC_VBB pin and GND is connected to
the system ground plane. VCC_VBB is used to provide a
proper VBB output level if a single ended input is used. For
differential LVPECL input VCC_VBB can be either 3.3V or
5V.
Under open input conditions, the D input will be biased
at a VCC/2 voltage level and the D input will be pulled to
GND. This condition will force the "Q" output low, ensuring
stability.
FEATURES
TRIPLE LVPECL-TO-PECL
OR PECL-TO-LVPECL
TRANSLATOR
SY100EL92
Rev.: D Amendment: /0
Issue Date: January, 1999
Function Vcc Vcco Vcc_VBB
PECL-to-LVPECL 5.0V 3.3V 5.0V
LVPECL-to-PECL 5.0V 5.0V 3.3V
PECL-to-PECL 5.0V 5.0V 5.0V
LVPECL-to-LVPECL 5.0V 3.3V 3.3V
FUNCTION TABLE
Pin Function
Dn PECL / LVPECL Inputs
Qn PECL / LVPECL Outputs
VBB PECL / LVPECL Reference Voltage Output
VCCO VCC for Output
VCC_VBB VCC for VBB Output
GND Common Ground Rail
V
CC VCC for Internal Circuitry
PIN NAMES
PIN CONFIGURATION/BLOCK DIAGRAM
SOIC
TOP VIEW
V
CC_
V
B
V
B
V
B
V
CC
V
CCO
V
CCO
V
CC
D
D
1
D
1
2
3
4
5
6
7
8
9
10 11
12
13
14
15
16
17
18
19
20
D
2
GND
Q
0
Q
0
Q
1
Q
2
Q
1
Q
2
D
1
D
1
