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SN74CBTLV3125PWR

Part # SN74CBTLV3125PWR
Description LV QUADRUPLE FET BUS SWITCH -Tape and Reel
Category Microcircuit
Availability In Stock
Qty 1269
Qty Price
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267 - 532 $0.11324
533 - 799 $0.10677
800 - 1,065 $0.09922
1,066 + $0.08844
Manufacturer Available Qty
Texas Instruments
Date Code: 0623
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Technical Document


DISCLAIMER: The information provided herein is solely for informational purposes. Customers must be aware of the suitability of this product for their application, and consider that variable factors such as Manufacturer, Product Category, Date Codes, Pictures and Descriptions may differ from available inventory.


    
SCDS037J − DECEMBER 1997 − REVISED OCTOBER 2003
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251−1443
D Standard ’125-Type Pinout
D 5- Switch Connection Between Two Ports
D Rail-to-Rail Switching on Data I/O Ports
D I
off
Supports Partial-Power-Down Mode
Operation
D Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
D, DGV, NS, OR PW PACKAGE
(TOP VIEW)
NC − No internal connection
DBQ PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
NC
1OE
1A
1B
2OE
2A
2B
GND
V
CC
4OE
4A
4B
3OE
3A
3B
NC
1
2
3
4
5
6
7
14
13
12
11
10
9
8
1OE
1A
1B
2OE
2A
2B
GND
V
CC
4OE
4A
4B
3OE
3A
3B
RGY PACKAGE
(TOP VIEW)
114
78
2
3
4
5
6
13
12
11
10
9
4OE
4A
4B
3OE
3A
1A
1B
2OE
2A
2B
1OE
3B
V
GND
CC
description/ordering information
The SN74CBTLV3125 quadruple FET bus switch features independent line switches. Each switch is disabled
when the associated output-enable (OE
) input is high.
This device is fully specified for partial-power-down applications using I
off
. The I
off
feature ensures that
damaging current will not backflow through the device when it is powered down. The device has isolation during
power off.
To ensure the high-impedance state during power up or power down, OE
should be tied to V
CC
through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
ORDERING INFORMATION
T
A
PACKAGE
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
QFN − RGY Tape and reel SN74CBTLV3125RGYR CL125
SOIC − D
Tube SN74CBTLV3125D
CBTLV3125
SOIC − D
Tape and reel SN74CBTLV3125DR
CBTLV3125
−40°C to 85°C
SOP − NS Tape and reel SN74CBTLV3125NSR CBTLV3125
−40 C to 85 C
SSOP (QSOP) − DBQ Tape and reel SN74CBTLV3125DBQR CL125
TSSOP − PW Tape and reel SN74CBTLV3125PWR CL125
TVSOP − DGV Tape and reel SN74CBTLV3125DGVR CL125
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines
are available at www.ti.com/sc/package.
Copyright 2003, Texas Instruments Incorporated
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Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

    
SCDS037J − DECEMBER 1997 − REVISED OCTOBER 2003
2
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251−1443
FUNCTION TABLE
(each bus switch)
INPUT
OE
FUNCTION
L A port = B port
H Disconnect
logic diagram (positive logic)
1A
1OE
SW
1B
2A
2OE
SW
2B
3A
3OE
SW
3B
4A
4OE
SW
4B
2
1
5
4
3
6
9
10
12
13
8
11
Pin numbers shown are for the D, DGV, NS, PW, and RGY packages.
simplified schematic, each FET switch
A
(OE)
B

    
SCDS037J − DECEMBER 1997 − REVISED OCTOBER 2003
3
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251−1443
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
CC
−0.5 V to 4.6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, V
I
(see Note 1) −0.5 V to 4.6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous channel current 128 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, I
IK
(V
I/O
< 0) −50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance, θ
JA
(see Note 2): D package 86°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
(see Note 2): DBQ package 90°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
(see Note 2): DGV package 127°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
(see Note 2): NS package 76°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
(see Note 2): PW package 113°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
(see Note 3): RGY package 47°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
stg
−65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
3. The package thermal impedance is calculated in accordance with JESD 51-5.
recommended operating conditions (see Note 4)
MIN MAX UNIT
V
CC
Supply voltage 2.3 3.6 V
V
IH
High-level control input voltage
V
CC
= 2.3 V to 2.7 V 1.7
V
V
IH
High-level control input voltage
V
CC
= 2.7 V to 3.6 V
2
V
V
IL
Low-level control input voltage
V
CC
= 2.3 V to 2.7 V 0.7
V
V
IL
Low-level control input voltage
V
CC
= 2.7 V to 3.6 V
0.8
V
T
A
Operating free-air temperature −40 85 °C
NOTE 4: All unused control inputs of the device must be held at V
CC
or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
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