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CY7C199-15DMB

Part # CY7C199-15DMB
Description SRAM Chip Async Single 5V 256K-Bit 32K x 8 15ns 28-Pin CDI
Category Microcircuit
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CYPRESS SEMICONDUCTOR
Date Code: 0047
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Technical Document


DISCLAIMER: The information provided herein is solely for informational purposes. Customers must be aware of the suitability of this product for their application, and consider that variable factors such as Manufacturer, Product Category, Date Codes, Pictures and Descriptions may differ from available inventory.

CY7C199
32K x 8 Static RAM
Cypress Semiconductor Corporation 3901 North First Street San Jose, CA 95134 408-943-2600
Document #: 38-05160 Rev. *A Revised January 7, 2003
Features
High speed
10 ns
•Fast t
DOE
CMOS for optimum speed/power
Low active power
467 mW (max, 12 ns “L” version)
Low standby power
0.275 mW (max, “L” version)
2V data retention (“L” version only)
Easy memory expansion with CE
and OE features
TTL-compatible inputs and outputs
Automatic power-down when deselected
Functional Description
The CY7C199 is a high-performance CMOS static RAM
organized as 32,768 words by 8 bits. Easy memory expansion
is provided by an active LOW Chip Enable (CE
) and active
LOW Output Enable (OE
) and three-state drivers. This device
has an automatic power-down feature, reducing the power
consumption by 81% when deselected. The CY7C199 is in the
standard 300-mil-wide DIP, SOJ, and LCC packages.
An active LOW Write Enable signal (WE
) controls the
writing/reading operation of the memory. When CE
and WE
inputs are both LOW, data on the eight data input/output pins
(I/O
0
through I/O
7
) is written into the memory location
addressed by the address present on the address pins (A
0
through A
14
). Reading the device is accomplished by selecting
the device and enabling the outputs, CE
and OE active LOW,
while WE
remains inactive or HIGH. Under these conditions,
the contents of the location addressed by the information on
address pins are present on the eight data input/output pins.
The input/output pins remain in a high-impedance state unless
the chip is selected, outputs are enabled, and Write Enable
(WE
) is HIGH. A die coat is used to improve alpha immunity.
Logic Block Diagram
Pin Configurations
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
COLUMN
DECODER
ROW DECODER
SENSE AMPS
INPUT BUFFER
POWER
DOWN
WE
OE
I/O
0
CE
I/O
1
I/O
2
I/O
3
1
2
3
4
5
6
7
8
9
10
11
14
15
16
20
19
18
17
21
24
23
22
Top View
DIP / SOJ / SOIC
12
13
25
28
27
26
GND
A
6
A
7
A
8
A
9
A
10
A
11
A
12
A
13
WE
V
CC
A
4
A
3
A
2
A
1
I/O
7
I/O
6
I/O
5
I/O
4
A
14
A
5
I/O
0
I/O
1
I/O
2
CE
OE
A
0
I/O
3
1024 x 32 x 8
ARRAY
I/O
7
I/O
6
I/O
5
I/O
4
A
9
A
0
A
11
A
13
A
12
A
14
A
10
28
4
5
6
7
8
9
10
321 27
1314151617
26
25
24
23
22
21
20
11
12
19
18
A
7
V
CC
I/O
5
GND
WE
A
6
A
5
I/O
4
I/O
3
I/O
2
A
8
A
9
A
10
A
11
A
12
A
13
A
14
CE
A
3
A
2
A
1
A
0
I/O
1
I/O
7
I/O
6
A
4
OE
I/O
0
Top View
LCC
22
23
24
25
26
27
28
1
2
5
10
11
15
14
13
12
16
19
18
17
3
4
20
21
7
6
8
9
OE
A
1
A
2
A
3
A
4
WE
V
CC
A
5
A
6
A
7
A
8
A
9
A
0
CE
I/O
7
I/O
6
I/O
5
GND
I/O
2
I/O
1
I/O
4
I/O
0
A
14
A
10
A
11
A
13
A
12
I/O
3
TSOP I
Top View
(not to scale)
Selection Guide
7C199
-8
7C199
-10
7C199
-12
7C199
-15
7C199
-20
7C199
-25
7C199
-35
7C199
-45 Unit
Maximum Access Time 81012 15 20 25 35 45 ns
Maximum Operating Current 120 110 160 155 150 150 140 140 mA
L 90 90 90 90 80 70
Maximum CMOS Standby Current 0.5 0.5 10 10 10 10 10 10 mA
L 0.05 0.05 0.05 0.05 0.05 0.05
Shaded area contains advance information.
CY7C199
Document #: 38-05160 Rev. *A Page 2 of 13
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature .................................65°C to +150°C
Ambient Temperature with
Power Applied.............................................55°C to +125°C
Supply Voltage to Ground Potential
(Pin 28 to Pin 14) ........................................... 0.5V to +7.0V
DC Voltage Applied to Outputs
in High-Z State
[1]
....................................0.5V to V
CC
+ 0.5V
DC Input Voltage
[1]
.................................0.5V to V
CC
+ 0.5V
Output Current into Outputs (LOW).............................20 mA
Static Discharge Voltage.......................................... > 2001V
(per MIL-STD-883, Method 3015)
Latch-up Current.................................................... > 200 mA
Operating Range
Range Ambient Temperature
[2]
V
CC
Commercial 0°C to +70°C 5V ± 10%
Industrial 40°C to +85°C 5V ± 10%
Military 55°C to +125°C 5V ± 10%
Electrical Characteristics Over the Operating Range (-8, -10, -12, -15)
[3]
Parameter Description Test Conditions
7C199-8 7C199-10 7C199-12 7C199-15
Unit
Min. Max. Min. Max. Min. Max. Min. Max.
V
OH
Output HIGH Voltage V
CC
= Min., I
OH
=4.0 mA 2.4 2.4 2.4 2.4 V
V
OL
Output LOW Voltage V
CC
= Min., I
OL
=8.0 mA 0.40.40.40.4V
V
IH
Input HIGH Voltage 2.2 V
CC
+0.3V
2.2 V
CC
+0.3V
2.2 V
CC
+0.3V
2.2 V
CC
+0.3V
V
V
IL
Input LOW Voltage 0.5 0.8 0.5 0.8 0.5 0.8 0.5 0.8 V
I
IX
Input Load Current GND < V
I
< V
CC
5 +5 5+55+55+5µA
I
OZ
Output Leakage Current GND < V
O
< V
CC
, Output
Disabled
5 +5 5+55+55+5µA
I
CC
V
CC
Operating Supply
Current
V
CC
= Max.,
I
OUT
= 0 mA,
f = f
MAX
= 1/t
RC
Coml 120 110 160 155 mA
L
85 85 100 mA
Mil 180 mA
I
SB1
Automatic CE
Power-down Current
TTL Inputs
Max. V
CC
, CE >
V
IH
, V
IN
> V
IH
or
V
IN
< V
IL
, f = f
MAX
Coml 5 5 30 30 mA
L
555mA
I
SB2
Automatic CE
Power-down Current
CMOS Inputs
Max. V
CC
,
CE > V
CC
0.3V
V
IN
> V
CC
0.3V
or V
IN
< 0.3V, f = 0
Coml
0.5 0.5 10 10 mA
L
0.05 0.05 0.05 0.05 mA
Mil
15 mA
Electrical Characteristics Over the Operating Range (-20, -25, -35, -45)
[3]
Parameter Description Test Conditions
7C199-20 7C199-25 7C199-35 7C199-45
UnitMin. Max. Min. Max. Min. Max. Min. Max.
V
OH
Output HIGH Voltage V
CC
= Min., I
OH
= 4.0 mA 2.4 2.4 2.4 2.4 V
V
OL
Output LOW Voltage V
CC
= Min., I
OL
= 8.0 mA 0.4 0.4 0.4 0.4 V
V
IH
Input HIGH Voltage 2.2 V
CC
+0.3V
2.2 V
CC
+0.3V
2.2 V
CC
+0.3V
2.2 V
CC
+0.3V
V
V
IL
Input LOW Voltage 0.5 0.8 -0.5 0.8 -0.5 0.8 -0.5 0.8 V
I
IX
Input Load Current GND < V
I
< V
CC
5+55+55+5 5+5µA
I
OZ
Output Leakage Current GND < V
I
< V
CC
, Output
Disabled
5+55+55+5 5+5µA
I
CC
V
CC
Operating Supply
Current
V
CC
= Max.,
I
OUT
= 0 mA,
f = f
MAX
= 1/t
RC
Coml 150 150 140 140 mA
L90807070mA
Mil 170 150 150 150 mA
Shaded area contains advance information.
Notes:
1. V
IL
(min.) = 2.0V for pulse durations of less than 20 ns.
2. T
A
is the instant on case temperature.
3. See the last page of this specification for Group A subgroup testing information.
CY7C199
Document #: 38-05160 Rev. *A Page 3 of 13
I
SB1
Automatic CE
Power-down Current
TTL Inputs
Max. V
CC
, CE > V
IH
,
V
IN
> V
IH
or V
IN
< V
IL
,
f = f
MAX
Coml30 30 25 25mA
L5555mA
I
SB2
Automatic CE
Power-down Current
CMOS Inputs
Max. V
CC
,
CE
> V
CC
0.3V
V
IN
> V
CC
0.3V or
V
IN
< 0.3V, f=0
Coml10 10 10 10mA
L 0.05 0.05 0.05 0.05 µA
Mil 15 15 15 15 mA
Electrical Characteristics Over the Operating Range (-20, -25, -35, -45) (continued)
[3]
Parameter Description Test Conditions
7C199-20 7C199-25 7C199-35 7C199-45
UnitMin. Max. Min. Max. Min. Max. Min. Max.
Capacitance
[4 ]
Parameter Description Test Conditions Max. Unit
C
IN
Input Capacitance T
A
= 25°C, f = 1 MHz,
V
CC
= 5.0V
8pF
C
OUT
Output Capacitance 8 pF
AC Test Loads and Waveforms
[5]
Data Retention Characteristics Over the Operating Range (L-version only)
Parameter Description Conditions
[6]
Min. Max. Unit
V
DR
V
CC
for Data Retention 2.0 V
I
CCDR
Data Retention Current Coml V
CC
= V
DR
= 2.0V, CE > V
CC
0.3V, V
IN
> V
CC
0.3V or V
IN
<
0.3V
µA
Coml L 10 µA
t
CDR
[4]
Chip Deselect to Data Retention Time 0 ns
t
R
[5]
Operation Recovery Time 200 µs
3.0V
5V
OUTPUT
R1 481
R2
255
30 pF
INCLUDING
JIG AND
SCOPE
GND
90%
10%
90%
10%
t
r
t
r
5V
OUTPUT
R1 481
R2
255
5pF
INCLUDING
JIG AND
SCOPE
(a) (b)
OUTPUT 1.73V
Equivalent to: THÉ VENIN EQUIVALENT
ALL INPUT PULSES
167
Data Retention Waveform
Note:
4. Tested initially and after any design or process changes that may affect these parameters.
5. t
R
< 3 ns for the -12 and the -15 speeds. t
R
< 5 ns for the -20 and slower speeds
6. No input may exceed V
CC
+ 0.5V.
3.0V3.0V
t
CDR
V
DR
> 2V
DATA RETENTION MODE
t
R
CE
V
CC
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