Philips Semiconductors Product specification
74F646/A/74F648/ATransceivers/registers
2
1990 Sep 25 853-1124 00515
FEATURES
• Combines 74F245 and two 74F374 type functions in one chip
• High impedance base inputs for reduced loading (70µA in high
and low states)
• Independent registers for A and B buses
• Multiplexed real-time and stored data
• Choice of non-inverting and inverting data paths
• Controlled ramp outputs for 74F646A/74F648A
• 3-state outputs
• 300 mil wide 24-pin slim dip package
DESCRIPTION
The 74F646/74F646A and 74F648/74F648A transceivers/registers
consist of bus transceiver circuits with 3–state outputs, D–type
flip–flops, and control circuitry arranged for multiplexed transmission
of data directly from the input bus or the internal registers. Data on
the A or B bus will be clocked into the registers as the appropriate
clock pin goes high. Output enable (OE
) and DIR pins are provided
to control the transceiver function. In the transceiver mode, data
present at the high impedance port may be stored in either the A or
B register or both.
The select (SAB, SBA) pins determine whether data is stored or
transferred through the device in real–time. The DIR determines
which bus will receive data when the OE
is active low. In the
isolation mode (OE
= high), data from bus A may be stored in the B
register and/or data from bus B may be stored in the A register.
When an output function is disabled, the input function is still
enabled and may be used to store and transmit data. Only one of
the two buses, A or B may be driven at a time.
TYPE
TYPICAL f
max
TYPICAL SUPPLY CURRENT ( TOTAL)
74F646/74F648 115MHz 140mA
74F646A/74F648A 185MHz 105mA
ORDERING INFORMATION
ORDER CODE
DESCRIPTION COMMERCIAL RANGE PKG DWG #
V
CC
= 5V ±10%, T
amb
= 0°C to +70°C
24–pin plastic slim DIP
(300mil)
N74F646N, N74F646AN, N74F648N, N74F648AN SOT222-1
24–pin plastic SOL N74F646D, N74F646AD, N74F648D, N74F648AD SOT137-1
INPUT AND OUTPUT LOADING AND FAN OUT TABLE
PINS DESCRIPTION
74F (U.L.) HIGH/
LOW
LOAD VALUE HIGH/
LOW
A0 – A7, B0 – B7 A and B inputs 3.5/0.116 70µA/70µA
CPAB A–to–B clock input 1.0/0.033 20µA/20µA
CPBA B–to–A clock input 1.0/0.033 20µA/20µA
SAB A–to–B select input 1.0/0.033 20µA/20µA
SBA B–to–A select input 1.0/0.033 20µA/20µA
DIR Data flow directional control enable input 1.0/0.033 20µA/20µA
OE Output enable input 1.0/0.033 20µA/20µA
A0 – A7, B0 – B7 A, B outputs for N74F646A/N74F648A 750/80 15mA/48mA
A0 – A7, B0 – B7 A, B outputs for N74F646/N74F648 750/106.7 15mA/64mA
NOTE: One (1.0) FAST unit load is defined as: 20µA in the high state and 0.6mA in the low state.
