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Dual-Core Intel® Xeon® Processor 3000 Series Datasheet 27

Electrical Specifications

2.7.2 CMOS and Open Drain Signals

Legacy input signals such as A20M#, IGNNE#, INIT#, SMI#, and STPCLK# use CMOS

input buffers. All of the CMOS and Open Drain signals are required to be asserted/de-

asserted for at least four BCLKs in order for the processor to recognize the proper

signal state. See Section 2.7.3 for the DC. See Section 6.2 for additional timing

requirements for entering and leaving the low power states.

2.7.3 Processor DC Specifications

The processor DC specifications in this section are defined at the processor core (pads)

unless otherwise stated. All specifications apply to all frequencies and cache sizes

unless otherwise stated.

Table 2-11. GTL+ Signal Group DC Specifications

Symbol Parameter Min Max Unit Notes

Notes:

1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.

Input Low Voltage -0.10 GTLREF – 0.10 V

2, 3

2. V

is defined as the voltage range at a receiving agent that will be interpreted as a logical low value.

3. The V

referred to in these specifications is the instantaneous V

Input High Voltage GTLREF + 0.10 V

+ 0.10 V

4, 5, 3

4. V

is defined as the voltage range at a receiving agent that will be interpreted as a logical high value.

5. V

and V

may experience excursions above V

Output High Voltage V

– 0.10 V

5, 3

Output Low Current N/A V

TT_MAX

/[(R

TT_MIN

)+(2*R

ON_

MIN

)]

A-

Input Leakage Current N/A ± 100 µA

6. Leakage to V

with land held at V

Output Leakage Current N/A ± 100 µA

7. Leakage to V

with land held at 300 mV.

Buffer On Resistance 10 13 Ω

Table 2-12. Open Drain and TAP Output Signal Group DC Specifications

Symbol Parameter Min Max Unit Notes

Notes:

1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.

Output Low Voltage 0 0.20 V -

Output High Voltage

–

0.05

2. V

is determined by the value of the external pull-up resister to V

. Refer to theappropriate platform design

guide for details.

Output Low Current 16 50 mA

3. Measured at V

* 0.2.

Output Leakage Current N/A ± 200 µA

4. For Vin between 0 and V

Electrical Specifications

28 Dual-Core Intel® Xeon® Processor 3000 Series Datasheet

Note:

1. V

supplies the PECI interface. PECI behavior does not affect V

min/max specifications.

2. The leakage specification applies to powered devices on the PECI bus.

3. The input buffers use a Schmitt-triggered input design for improved noise immunity.

Table 2-13. CMOS Signal Group DC Specifications

Symbol Parameter Min Max Unit Notes

Notes:

1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.

Input Low Voltage -0.10 V

* 0.30 V

2, 3

2. V

is defined as the voltage range at a receiving agent that will be interpreted as a logical low value.

3. The V

referred to in these specifications refers to instantaneous V

Input High Voltage V

* 0.70 V

+ 0.10 V

3, 4, 5

4. V

is defined as the voltage range at a receiving agent that will be interpreted as a logical high value.

5. V

and V

may experience excursions above V

Output Low Voltage -0.10 V

* 0.10 V

Output High Voltage 0.90 * V

+ 0.10 V

3, 6, 5

6. All outputs are open drain.

Output Low Current 1.70 4.70 mA

3, 7

7. I

is measured at 0.10 * V

TT.

is measured at 0.90 * V

TT.

Output High Current 1.70 4.70 mA

3, 7

Input Leakage Current N/A ± 100 µA

8. Leakage to V

with land held at V

Output Leakage Current N/A ± 100 µA

9. Leakage to V

with land held at 300 mV.

Table 2-14. PECI DC Electrical Limits

Symbol Definition and Conditions Min Max Units Notes

Input Voltage Range -0.15 V

+ 0.15 V

hysteresis

Hysteresis 0.1 * V

—V3

Negative-edge threshold voltage 0.275 * V

0.500 * V

Positive-edge threshold voltage 0.550 * V

0.725 * V

source

High level output source

= 0.75 * V

TT)

-6.0 N/A mA

sink

Low level output sink

= 0.25 * V

)

0.5 1.0 mA

leak+

High impedance state leakage to V

N/A 50 µA 2

leak-

High impedance leakage to GND N/A 10 µA 2

bus

Bus capacitance — 10 pF

noise

Signal noise immunity above 300 MHz 0.1 * V

—V

p-p

Dual-Core Intel® Xeon® Processor 3000 Series Datasheet 29

Electrical Specifications

2.7.3.1 GTL+ Front Side Bus Specifications

In most cases, termination resistors are not required as these are integrated into the

processor silicon. See Table 2-9 for details on which GTL+ signals do not include on-die

termination.

Valid high and low levels are determined by the input buffers by comparing with a

reference voltage called GTLREF. Table 2-15 lists the GTLREF specifications. The GTL+

reference voltage (GTLREF) should be generated on the system board using high

precision voltage divider circuits.

2.7.4 Clock Specifications

2.7.5 Front Side Bus Clock (BCLK[1:0]) and Processor Clocking

BCLK[1:0] directly controls the FSB interface speed as well as the core frequency of the

processor. As in previous generation processors, the processor’s core frequency is a

multiple of the BCLK[1:0] frequency. The processor bus ratio multiplier will be set at its

default ratio during manufacturing. Refer to Table 2-16 for the processor supported

ratios.

The processor uses a differential clocking implementation. For more information on the

processor clocking, contact your Intel Field representative. Platforms using a CK505

Clock Synthesizer/Driver should comply with the specifications in Section 2.7.8.

Platforms using a CK410 Clock Synthesizer/Driver should comply with the specifications

in Section 2.7.9.

Table 2-15. GTL+ Bus Voltage Definitions

Symbol Parameter Min Typ Max Units Notes

Notes:

1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.

GTLREF_PU GTLREF pull up resistor on

Mukilteo-2 (3000/3010) chipset

family boards

124 * 0.99 124 124 * 1.01 Ω

2. GTLREF is to be generated from V

by a voltage divider of 1% resistors (one divider for each GTLEREF land).

Refer to the applicable platform design guide for implementation details.

GTLREF_PD GTLREF pull down resistor on

Mukilteo-2 (3000/3010) chipset

family boards

210 * 0.99 210 210 * 1.01 Ω

GTLREF_PU GTLREF pull up resistor on

Bearlake chipset family boards

100 * 0.99 100 100 * 1.01 Ω

GTLREF_PD GTLREF pull down resistor on

Bearlake chipset family boards

200 * 0.99 200 200 * 1.01 Ω

Termination Resistance 45 50 55 Ω

3. R

is the on-die termination resistance measured at V

/3 of the GTL+ output driver. Refer to the appropriate

platform design guide for the board impedance. Refer to processor I/O buffer models for I/V characteristics.

COMP[3:0] COMP Resistance 49.40 49.90 50.40 Ω

4. COMP resistance must be provided on the system board with 1% resistors. See the applicable platform design

guide for implementation details. COMP[3:0] and COMP8 resistors are to V

COMP8 COMP Resistance 24.65 24.90 25.15 Ω

Part #	3000
Description	DUP RCPT PORTABLE OUTLET BX
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