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Electrical Specifications

24 Dual-Core Intel® Xeon® Processor 3000 Series Datasheet

2.6.3 V

Overshoot

The processor can tolerate short transient overshoot events where V

exceeds the VID

voltage when transitioning from a high to low current load condition. This overshoot

cannot exceed VID + V

OS_MAX

is the maximum allowable overshoot voltage).

The time duration of the overshoot event must not exceed T

OS_MAX

is the

maximum allowable time duration above VID). These specifications apply to the

processor die voltage as measured across the VCC_SENSE and VSS_SENSE lands.

Notes:

1. V

is measured overshoot voltage.

2. T

is measured time duration above VID.

2.6.4 Die Voltage Validation

Overshoot events on processor must meet the specifications in Table 2-7 when

measured across the VCC_SENSE and VSS_SENSE lands. Overshoot events that are

< 10 ns in duration may be ignored. These measurements of processor die level

overshoot must be taken with a bandwidth limited oscilloscope set to a greater than or

equal to 100 MHz bandwidth limit.

Table 2-7. V

Overshoot Specifications

Symbol Parameter Min Max Unit Figure Notes

OS_MAX

Magnitude of V

overshoot above VID — 50 mV 2-3

Notes:

1. Adherence to these specifications is required to ensure reliable processor operation.

OS_MAX

Time duration of V

overshoot above VID — 25 μs 2-3

Figure 2-3. V

Overshoot Example Waveform

Example Overshoot Waveform

0 5 10 15 20 25

Time [us]

Voltage [V]

VID - 0.000

VID + 0.050

: Overshoot time above VID

: Overshoot above VID

Dual-Core Intel® Xeon® Processor 3000 Series Datasheet 25

Electrical Specifications

2.7 Signaling Specifications

Most processor Front Side Bus signals use Gunning Transceiver Logic (GTL+) signaling

technology. This technology provides improved noise margins and reduced ringing

through low voltage swings and controlled edge rates. Platforms implement a

termination voltage level for GTL+ signals defined as V

. Because platforms implement

separate power planes for each processor (and chipset), separate V

and V

supplies

are necessary. This configuration allows for improved noise tolerance as processor

frequency increases. Speed enhancements to data and address busses have caused

signal integrity considerations and platform design methods to become even more

critical than with previous processor families.

The GTL+ inputs require a reference voltage (GTLREF) which is used by the receivers to

determine if a signal is a logical 0 or a logical 1. GTLREF must be generated on the

motherboard (see Table 2-15 for GTLREF specifications). Termination resistors (R

) for

GTL+ signals are provided on the processor silicon and are terminated to V

. Intel

chipsets will also provide on-die termination, thus eliminating the need to terminate the

bus on the motherboard for most GTL+ signals.

2.7.1 FSB Signal Groups

The front side bus signals have been combined into groups by buffer type. GTL+ input

signals have differential input buffers, which use GTLREF[1:0] as a reference level. In

this document, the term “GTL+ Input” refers to the GTL+ input group as well as the

GTL+ I/O group when receiving. Similarly, “GTL+ Output” refers to the GTL+ output

group as well as the GTL+ I/O group when driving.

With the implementation of a source synchronous data bus comes the need to specify

two sets of timing parameters. One set is for common clock signals which are

dependent upon the rising edge of BCLK0 (ADS#, HIT#, HITM#, etc.) and the second

set is for the source synchronous signals which are relative to their respective strobe

lines (data and address) as well as the rising edge of BCLK0. Asychronous signals are

still present (A20M#, IGNNE#, etc.) and can become active at any time during the

clock cycle. Table 2-8 identifies which signals are common clock, source synchronous,

and asynchronous.

Table 2-8. FSB Signal Groups (Sheet 1 of 2)

Signal Group Type Signals

GTL+ Common

Clock Input

Synchronous to

BCLK[1:0]

BPRI#, DEFER#, RESET#, RS[2:0]#, TRDY#

GTL+ Common

Clock I/O

Synchronous to

BCLK[1:0]

ADS#, BNR#, BPM[5:0]#, BR0#, DBSY#, DRDY#, HIT#, HITM#,

LOCK#

GTL+ Source

Synchronous I/O

Synchronous to

assoc. strobe

Signals Associated Strobe

REQ[4:0]#, A[16:3]#

ADSTB0#

A[35:17]#

ADSTB1#

D[15:0]#, DBI0# DSTBP0#, DSTBN0#

D[31:16]#, DBI1# DSTBP1#, DSTBN1#

D[47:32]#, DBI2# DSTBP2#, DSTBN2#

D[63:48]#, DBI3# DSTBP3#, DSTBN3#

Electrical Specifications

26 Dual-Core Intel® Xeon® Processor 3000 Series Datasheet

Notes:

1. Refer to Section 4.2 for signal descriptions.

2. In processor systems where no debug port is implemented on the system board, these signals are used to

support a debug port interposer. In systems with the debug port implemented on the system board, these

signals are no connects.

3. The value of these signals during the active-to-inactive edge of RESET# defines the processor configuration

options. See Section 6.1 for details.

4. PROCHOT# signal type is open drain output and CMOS input.

GTL+ Strobes Synchronous to

BCLK[1:0]

ADSTB[1:0]#, DSTBP[3:0]#, DSTBN[3:0]#

CMOS A20M#, IGNNE#, INIT#, LINT0/INTR, LINT1/NMI, SMI#,

STPCLK#, PWRGOOD, TCK, TDI, TMS, TRST#, BSEL[2:0],

VID[6:1]

Open Drain Output FERR#/PBE#, IERR#, THERMTRIP#, TDO

Open Drain

Input/Output

PROCHOT#

FSB Clock Clock BCLK[1:0], ITP_CLK[1:0]

Power/Other VCC, VTT, VCCA, VCCIOPLL, VCCPLL, VSS, VSSA, GTLREF[1:0],

COMP[8,3:0], RESERVED, TESTHI[13:0], VCC_SENSE,

VCC_MB_REGULATION, VSS_SENSE, VSS_MB_REGULATION,

DBR#

, VTT_OUT_LEFT, VTT_OUT_RIGHT, VTT_SEL, FCx, PECI,

MSID[1:0]

Table 2-8. FSB Signal Groups (Sheet 2 of 2)

Signal Group Type Signals

Table 2-9. Signal Characteristics

Signals with R

Signals with No R

A[35:3]#, ADS#, ADSTB[1:0]#, BNR#, BPRI#,

D[63:0]#, DBI[3:0]#, DBSY#, DEFER#, DRDY#,

DSTBN[3:0]#, DSTBP[3:0]#, HIT#, HITM#, LOCK#,

PROCHOT#, REQ[4:0]#, RS[2:0]#, TRDY#

A20M#, BCLK[1:0], BSEL[2:0], COMP[8,3:0],

IGNNE#, INIT#, ITP_CLK[1:0], LINT0/INTR,

LINT1/NMI, MSID[1:0] PWRGOOD, RESET#, SMI#,

STPCLK#, TESTHI[13:0], VID[6:1], GTLREF[1:0],

TCK, TDI, TMS, TRST#, VTT_SEL

Open Drain Signals

Notes:

1. Signals that do not have R

, nor are actively driven to their high-voltage level.

THERMTRIP#, FERR#/PBE#, IERR#, BPM[5:0]#, BR0#,

TDO, FCx

Table 2-10. Signal Reference Voltages

GTLREF V

BPM[5:0]#, RESET#, BNR#, HIT#, HITM#, BR0#,

A[35:0]#, ADS#, ADSTB[1:0]#, BPRI#, D[63:0]#,

DBI[3:0]#, DBSY#, DEFER#, DRDY#, DSTBN[3:0]#,

DSTBP[3:0]#, LOCK#, REQ[4:0]#, RS[2:0]#, TRDY#

A20M#, LINT0/INTR, LINT1/NMI, IGNNE#,

INIT#, PROCHOT#, PWRGOOD

, SMI#,

STPCLK#, TCK

, TDI

, TMS

, TRST#

Notes:

1. These signals also have hysteresis added to the reference voltage. See Table 2-12 for more information.

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Description	DUP RCPT PORTABLE OUTLET BX
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3000

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