Dual-Core Intel® Xeon® Processor 3000 Series Datasheet 21
Electrical Specifications
Notes:
1. Unless otherwise noted, all specifications in this table are based on estimates and simulations or empirical data. These
specifications will be updated with characterized data from silicon measurements at a later date.
2. Adherence to the voltage specifications for the processor are required to ensure reliable processor operation.
3. Each processor is programmed with a maximum valid voltage identification value (VID), which is set at manufacturing and can
not be altered. Individual maximum VID values are calibrated during manufacturing such that two processors at the same
frequency may have different settings within the VID range. Note this differs from the VID employed by the processor during a
power management event (Thermal Monitor 2, Enhanced Intel SpeedStep
®
Technology, or Extended HALT State).
4. These voltages are targets only. A variable voltage source should exist on systems in the event that a different voltage is required.
See Section 2.3 and Table 2-1 for more information.
5. The voltage specification requirements are measured across VCC_SENSE and VSS_SENSE lands at the socket with a 100 MHz
bandwidth oscilloscope, 1.5 pF maximum probe capacitance, and 1 MΩ minimum impedance. The maximum length of ground
wire on the probe should be less than 5 mm. Ensure external noise from the system is not coupled into the oscilloscope probe.
6. Refer to Table 2-5 and Figure 2-1 for the minimum, typical, and maximum V
CC
allowed for a given current. The processor should
not be subjected to any V
CC
and I
CC
combination wherein V
CC
exceeds V
CC_MAX
for a given current.
7. I
CC_MAX
specification is based on the V
CC_MAX
loadline. Refer to Figure 2-1 for details.
8. V
TT
must be provided via a separate voltage source and not be connected to V
CC
. This specification is measured at the land.
9. Baseboard bandwidth is limited to 20 MHz.
10.This is maximum total current drawn from V
TT
plane by only the processor. This specification does not include the current coming
from RTT (through the signal line). Refer to the Voltage Regulator-Down (VRD) 11.0 Processor Power Delivery Design Guidelines
For Desktop LGA775 Socket to determine the total I
TT
drawn by the system. This parameter is based on design characterization
and is not tested.
Table 2-5. V
CC
Static and Transient Tolerance for Processors with 4 MB L2 Cache
I
CC
(A)
Voltage Deviation from VID Setting (V)
1, 2, 3, 4
Notes:
1. The loadline specification includes both static and transient limits except for overshoot allowed as shown in
Section 2.6.3.
2. This table is intended to aid in reading discrete points on Figure 2-1.
3. The loadlines specify voltage limits at the die measured at the VCC_SENSE and VSS_SENSE lands. Voltage
regulation feedback for voltage regulator circuits must be taken from processor VCC and VSS lands. Refer to
the Voltage Regulator-Down (VRD) 11.0 Processor Power Delivery Design Guidelines For Desktop LGA775
Socket for socket loadline guidelines and VR implementation details.
4. Adherence to this loadline specification is required to ensure reliable processor operation.
Maximum Voltage
1.30 mΩ
Typical Voltage
1.425 mΩ
Minimum Voltage
1.55 mΩ
0 0.000 -0.019 -0.038
5 -0.007 -0.026 -0.046
10 -0.013 -0.033 -0.054
15 -0.020 -0.040 -0.061
20 -0.026 -0.048 -0.069
25 -0.033 -0.055 -0.077
30 -0.039 -0.062 -0.085
35 -0.046 -0.069 -0.092
40 -0.052 -0.076 -0.100
45 -0.059 -0.083 -0.108
50 -0.065 -0.090 -0.116
55 -0.072 -0.097 -0.123
60 -0.078 -0.105 -0.131
65 -0.085 -0.112 -0.139
70 -0.091 -0.119 -0.147
75 -0.098 -0.126 -0.154
