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Electrical Specifications

18 Dual-Core Intel® Xeon® Processor 3000 Series Datasheet

2.4 Market Segment Identification (MSID)

The MSID[1:0] signals may be used as outputs to determine the Market Segment of

the processor. Table 2-2 provides details regarding the state of MSID[1:0]. A circuit can

be used to prevent 130 W TDP processors from booting on boards optimized for

65 W TDP.

Notes:

1. The MSID[1:0] signals are provided to indicate the Market Segment for the processor and may be used for

future processor compatibility or for keying. Circuitry on the motherboard may use these signals to identify

the processor installed.

2. These signals are not connected to the processor die.

3. A logic 0 is achieved by pulling the signal to ground on the package.

4. A logic 1 is achieved by leaving the signal as a no connect on the package.

2.5 Reserved, Unused, and TESTHI Signals

All RESERVED lands must remain unconnected. Connection of these lands to V

, V

, or to any other signal (including each other) can result in component malfunction

or incompatibility with future processors. See Chapter 4 for a land listing of the

processor and the location of all RESERVED lands.

In a system level design, on-die termination has been included by the processor to

allow signals to be terminated within the processor silicon. Most unused GTL+ inputs

should be left as no connects as GTL+ termination is provided on the processor silicon.

However, see Table 2-8 for details on GTL+ signals that do not include on-die

termination.

Unused active high inputs, should be connected through a resistor to ground (V

Unused outputs can be left unconnected, however this may interfere with some TAP

functions, complicate debug probing, and prevent boundary scan testing. A resistor

must be used when tying bidirectional signals to power or ground. When tying any

signal to power or ground, a resistor will also allow for system testability. Resistor

values should be within ± 20% of the impedance of the motherboard trace for front

side bus signals. For unused GTL+ input or I/O signals, use pull-up resistors of the

same value as the on-die termination resistors (R

). For details, see Table 2-15.

TAP and CMOS signals do not include on-die termination. Inputs and used outputs must

be terminated on the motherboard. Unused outputs may be terminated on the

motherboard or left unconnected. Note that leaving unused outputs unterminated may

interfere with some TAP functions, complicate debug probing, and prevent boundary

scan testing.

All TESTHI[13:0] lands should be individually connected to V

via a pull-up resistor

that matches the nominal trace impedance.

Table 2-2. Market Segment Selection Truth Table for MSID[1:0]

1, 2, 3, 4

MSID1 MSID0 Description

00Dual-Core Intel

Xeon

processor 3000 series

01Reserved

10Reserved

11Reserved

Dual-Core Intel® Xeon® Processor 3000 Series Datasheet 19

Electrical Specifications

The TESTHI signals may use individual pull-up resistors or be grouped together as

detailed below. A matched resistor must be used for each group:

• TESTHI[1:0]

• TESTHI[7:2]

• TESTHI8/FC42 – cannot be grouped with other TESTHI signals

• TESTHI9/FC43 – cannot be grouped with other TESTHI signals

• TESTHI10 – cannot be grouped with other TESTHI signals

• TESTHI11 – cannot be grouped with other TESTHI signals

• TESTHI12/FC44 – cannot be grouped with other TESTHI signals

• TESTHI13 – cannot be grouped with other TESTHI signals

However, utilization of boundary scan test will not be functional if these lands are

connected together. For optimum noise margin, all pull-up resistor values used for

TESTHI[13:0] lands should have a resistance value within ± 20% of the impedance of

the board transmission line traces. For example, if the nominal trace impedance is 50 Ω,

then a value between 40 Ω and 60 Ω should be used.

2.6 Voltage and Current Specification

2.6.1 Absolute Maximum and Minimum Ratings

Table 2-3 specifies absolute maximum and minimum ratings only and lie outside the

functional limits of the processor. Within functional operation limits, functionality and

long-term reliability can be expected.

At conditions outside functional operation condition limits, but within absolute

maximum and minimum ratings, neither functionality nor long-term reliability can be

expected. If a device is returned to conditions within functional operation limits after

having been subjected to conditions outside these limits, but within the absolute

maximum and minimum ratings, the device may be functional, but with its lifetime

degraded depending on exposure to conditions exceeding the functional operation

condition limits.

At conditions exceeding absolute maximum and minimum ratings, neither functionality

nor long-term reliability can be expected. Moreover, if a device is subjected to these

conditions for any length of time then, when returned to conditions within the

functional operating condition limits, it will either not function, or its reliability will be

severely degraded.

Although the processor contains protective circuitry to resist damage from static

electric discharge, precautions should always be taken to avoid high static voltages or

electric fields.

Electrical Specifications

20 Dual-Core Intel® Xeon® Processor 3000 Series Datasheet

2.6.2 DC Voltage and Current Specification

Table 2-3. Absolute Maximum and Minimum Ratings

Symbol Parameter Min Max Unit Notes

1, 2

Notes:

1. For functional operation, all processor electrical, signal quality, mechanical and thermal specifications must be

satisfied.

2. Excessive overshoot or undershoot on any signal will likely result in permanent damage to the processor.

Core voltage with respect to V

–0.3 1.55 V -

FSB termination voltage with respect to

–0.3 1.55 V -

Processor case temperature See

Chapter 5

See

Chapter 5

°C -

STORAGE

Processor storage temperature –40 85 °C

3, 4, 5

3. Storage temperature is applicable to storage conditions only. In this scenario, the processor must not receive

a clock, and no lands can be connected to a voltage bias. Storage within these limits will not affect the long-

term reliability of the device. For functional operation, refer to the processor case temperature specifications.

4. This rating applies to the processor and does not include any tray or packaging.

5. Failure to adhere to this specification can affect the long term reliability of the processor.

Table 2-4. Voltage and Current Specifications

Symbol Parameter Min Typ Max Unit Notes

1, 2

VID Range VID 0.8500 — 1.5 V

Processor Number

(4 MB L2 Cache)

3085

3075

3070

3065

3060

for

775_VR_CONFIG_06

3.00 GHz

2.66 GHz

2.33 GHz

2.40 GHz

Refer to Table 2-5 and

Figure 2-1

4, 5, 6

Processor Number

(2 MB L2 Cache)

3050

3040

for

775_VR_CONFIG_06

2.13 GHz

1.86 GHz

Refer to Table 2-6 and

Figure 2-2

CC_BOOT

Default V

voltage for initial power up — 1.10 — V

CCPLL

PLL V

- 5% 1.50 + 5%

Processor Number

3085

3075

3070

3065

3060

3050

3040

for

775_VR_CONFIG_06

3.00 GHz

2.66 GHz

2.33 GHz

2.40 GHz

2.13 GHz

1.86 GHz

——

FSB termination voltage

(DC + AC specifications)

1.14 1.20 1.26 V

VTT_OUT_LEFT and

VTT_OUT_RIGHT I

DC Current that may be drawn from

VTT_OUT_LEFT and VTT_OUT_RIGHT per pin

— — 580 mA

for V

supply before V

stable

for V

supply after V

stable

——4.5

4.6

CC_VCCPLL

for PLL land — — 130 mA

CC_GTLREF

for GTLREF — — 200 μA

Part #	3000
Description	DUP RCPT PORTABLE OUTLET BX
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3000

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