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Technical Document


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Features
90 Dual-Core Intel® Xeon® Processor 3000 Series Datasheet
6.2.1 Normal State
This is the normal operating state for the processor.
6.2.2 HALT and Extended HALT Powerdown States
The processor supports the HALT or Extended HALT powerdown state. The Extended
HALT Powerdown must be enabled via the BIOS for the processor to remain within its
specification. Refer to the Conroe Processor Family BIOS Writer's Guide (BWG) for
Extended HALT configuration information.
The Extended HALT state is a lower power state as compared to the Stop Grant State.
If Extended HALT is not enabled, the default Powerdown state entered will be HALT.
Refer to the following sections for details about the HALT and Extended HALT states.
6.2.2.1 HALT Powerdown State
HALT is a low power state entered when all the processor cores have executed the HALT
or MWAIT instructions. When one of the processor cores executes the HALT instruction,
that processor core is halted; however, the other processor continues normal operation.
The processor transitions to the Normal state upon the occurrence of SMI#, INIT#, or
LINT[1:0] (NMI, INTR). RESET# causes the processor to immediately initialize itself.
Figure 6-1. Processor Low Power State Machine
Normal State
- Normal Execution
Extended Stop Grant
State or Stop Grant State
- BCLK running
- Snoops and interrupts
allowed
Extended Stop Grant
Snoop or Stop Grant
Snoop State
-BCLK running
- Service Snoops to caches
Extended HALT Snoop or
HALT Snoop State
-BCLK running
- Service Snoops to caches
Extended HALT or HALT
State
-BCLK running
- Snoops and interrupts
allowed
HALT or MWAIT Instruction and
HALT Bus Cycle Generated
INIT#, INTR, NMI, SMI#, RESET#,
FSB interrupts
STPCLK#
Asserted
STPCLK#
De-asserted
STPCLK#
Asserted
STPCLK#
De-asserted
Snoop
Event
Occurs
Snoop
Event
Serviced
Snoop Event Occurs
Snoop Event Serviced
Dual-Core Intel® Xeon® Processor 3000 Series Datasheet 91
Features
The return from a System Management Interrupt (SMI) handler can be to either
Normal Mode or the HALT Power Down state. See the IA-32 Intel
®
Architecture
Software Developer's Manual Volume 3: System Programmer's Guide for more
information.
The system can generate a STPCLK# while the processor is in the HALT powerdown
state. When the system deasserts the STPCLK# interrupt, the processor will return
execution to the HALT state.
While in HALT powerdown state, the processor will process bus snoops.
6.2.2.2 Extended HALT Powerdown State
Extended HALT is a low power state entered when all processor cores have executed
the HALT or MWAIT instructions and Extended HALT has been enabled via the BIOS.
When one of the processor cores executes the HALT instruction, that logical processor
is halted; however, the other processor continues normal operation. The Extended
HALT Powerdown state must be enabled via the BIOS for the processor to remain within
its specification.
The processor automatically transitions to a lower frequency and voltage operating
point before entering the Extended HALT state. Note that the processor FSB frequency
is not altered; only the internal core frequency is changed. When entering the low
power state, the processor first switches to the lower bus ratio and then transitions to
the lower VID.
While in Extended HALT state, the processor processes bus snoops.
The processor exits the Extended HALT state when a break event occurs. When the
processor exits the Extended HALT state, it will resume operation at the lower
frequency, f
irst transition the VID to the original value and then change the bus ratio
back to the original value.
6.2.3 Stop Grant and Extended Stop Grant States
The processor supports the Stop Grant and Extended Stop Grant states. The Extended
Stop Grant state is a feature that must be configured and enabled via the BIOS. Refer
to the BIOS Writer’s Guide for Extended Stop Grant configuration information. Refer to
the following sections for details about the Stop Grant and Extended Stop Grant states.
6.2.3.1 Stop Grant State
When the STPCLK# signal is asserted, the Stop Grant state of the processor is entered
20 bus clocks after the response phase of the processor-issued Stop Grant
Acknowledge special bus cycle.
Since the GTL+ signals receive power from the FSB, these signals should not be driven
(allowing the level to return to V
TT
) for minimum power drawn by the termination
resistors in this state. In addition, all other input signals on the FSB should be driven to
the inactive state.
RESET# will cause the processor to immediately initialize itself, but the processor will
stay in Stop-Grant state. A transition back to the Normal state will occur with the de-
assertion of the STPCLK# signal.
Features
92 Dual-Core Intel® Xeon® Processor 3000 Series Datasheet
A transition to the Grant Snoop state will occur when the processor detects a snoop on
the FSB (see Section 6.2.4).
While in the Stop-Grant State, SMI#, INIT#, and LINT[1:0] will be latched by the
processor, and only serviced when the processor returns to the Normal State. Only one
occurrence of each event will be recognized upon return to the Normal state.
While in Stop-Grant state, the processor will process a FSB snoop.
6.2.3.2 Extended Stop Grant State
Extended Stop Grant is a low power state entered when the STPCLK# signal is asserted
and Extended Stop Grant has been enabled via the BIOS.
The processor will automatically transition to a lower frequency and voltage operating
point before entering the Extended Stop Grant state. When entering the low power
state, the processor will first switch to the lower bus ratio and then transition to the
lower VID.
The processor exits the Extended Stop Grant state when a break event occurs. When
the processor exits the Extended Stop Grant state, it will resume operation at the lower
frequency, transition the VID to the original value, and then change the bus ratio back
to the original value.
6.2.4 Extended HALT Snoop State, HALT Snoop State, Extended
Stop Grant Snoop State, and Stop Grant Snoop State
The Extended HALT Snoop State is used in conjunction with the new Extended HALT
state. If Extended HALT state is not enabled in the BIOS, the default Snoop State
entered will be the HALT Snoop State. Refer to the sections below for details on HALT
Snoop State, Stop Grant Snoop State and Extended HALT Snoop State, and Extended
Stop Grant Snoop State.
6.2.4.1 HALT Snoop State, Stop Grant Snoop State
The processor will respond to snoop transactions on the FSB while in Stop-Grant state
or in HALT Power Down state. During a snoop transaction, the processor enters the
HALT Snoop State:Stop Grant Snoop state. The processor will stay in this state until the
snoop on the FSB has been serviced (whether by the processor or another agent on the
FSB). After the snoop is serviced, the processor returns to the Stop Grant state or HALT
Power Down state, as appropriate.
6.2.4.2 Extended HALT Snoop State, Extended Stop Grant Snoop State
The Extended HALT Snoop State is the default Snoop State when the Extended HALT
state is enabled via the BIOS. The processor will remain in the lower bus ratio and VID
operating point of the Extended HALT state or Extended Stop Grant state. While in the
Extended HALT Snoop State or Extended Stop Grant Snoop State, snoops are handled
the same way as in the HALT Snoop State or Stop Grant Snoop State. After the snoop is
serviced, the processor will return to the Extended HALT state or Extended Stop Grant
state.
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