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Technical Document


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Dual-Core Intel® Xeon® Processor 3000 Series Datasheet 87
Thermal Specifications and Design Considerations
Figure 8. Conceptual Fan Control on Thermal Diode-Based Platforms
Min
Max
Fan Speed
(RPM)
T
CONTROL
Setting
TCC Activation
Temperature
T
DIODE
= 90 °C
T
DIODE
= 80 °C
T
DIODE
= 70 °C
Temperature
Thermal Specifications and Design Considerations
88 Dual-Core Intel® Xeon® Processor 3000 Series Datasheet
5.4.2 PECI Specifications
5.4.2.1 PECI Device Address
The PECI device address for socket 0 is 30h and socket 1 resides at 31h. Note that each
address also supports two domains (Domain 0 and Domain 1). For more information on
PECI domains, refer to the Platform Environment Control Interface Specification.
5.4.2.2 PECI Command Support
PECI command support is covered in detail in the Platform Environment Control
Interface Specification. Refer to this document for details on supported PECI command
function and codes.
5.4.2.3 PECI Fault Handling Requirements
PECI is largely a fault tolerant interface, including noise immunity and error checking
improvements over other comparable industry standard interfaces. The PECI client is
as reliable as the device that it is embedded in, and thus given operating conditions
that fall under the specification, the PECI will always respond to requests and the
protocol itself can be relied upon to detect any transmission failures. There are,
however, certain scenarios where the PECI is know to be unresponsive.
Prior to a power on RESET# and during RESET# assertion, PECI is not ensured to
provide reliable thermal data. System designs should implement a default power-on
condition that ensures proper processor operation during the time frame when reliable
data is not available via PECI.
To protect platforms from potential operational or safety issues due to an abnormal
condition on PECI, the Host controller should take action to protect the system from
possible damaging states. It is recommended that the PECI host controller take
appropriate action to protect the client processor device if valid temperature readings
have not been obtained in response to three consecutive gettemp()s or for a one
second time interval. The host controller may also implement an alert to software in the
event of a critical or continuous fault condition.
5.4.2.4 PECI GetTemp0() Error Code Support
The error codes supported for the processor GetTemp() command are listed in Table 8.
Table 8. GetTemp0() Error Codes
Error Code Description
8000h General sensor error
8002h
Sensor is operational, but has detected a temperature below its operational
range (underflow).
Dual-Core Intel® Xeon® Processor 3000 Series Datasheet 89
Features
6 Features
6.1 Power-On Configuration Options
Several configuration options can be configured by hardware. The processor samples
the hardware configuration at reset, on the active-to-inactive transition of RESET#. For
specifications on these options, refer to Table 6-1.
The sampled information configures the processor for subsequent operation. These
configuration options cannot be changed except by another reset. All resets reconfigure
the processor; for reset purposes, the processor does not distinguish between a
"warm" reset and a "power-on" reset.
6.2 Clock Control and Low Power States
The processor allows the use of AutoHALT and Stop-Grant states to reduce power
consumption by stopping the clock to internal sections of the processor, depending on
each particular state. See Figure 6-1 for a visual representation of the processor low
power states.
Table 6-1. Power-On Configuration Option Signals
Configuration Option Signal
1
,
2
,
3
Notes:
1. Asserting this signal during RESET# will select the corresponding option.
2. Address signals not identified in this table as configuration options should not be asserted
during RESET#.
3. Disabling of any of the cores within the processor must be handled by configuring the
EXT_CONFIG Model Specific Register (MSR). This MSR will allow for the disabling of a single
core.
Output tristate SMI#
Execute BIST A3#
Disable dynamic bus parking A25#
Symmetric agent arbitration ID BR0#
RESERVED A[8:5]#, A[24:11]#, A[35:26]#
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