Land Listing and Signal Descriptions
68 Dual-Core Intel® Xeon® Processor 3000 Series Datasheet
4.2 Alphabetical Signals Reference
Table 4-3. Signal Description (Sheet 1 of 7)
Name Type Description
A[35:3]# Input/Output A[35:3]# (Address) define a 2
36
-byte physical memory address
space. In sub-phase 1 of the address phase, these signals transmit the
address of a transaction. In sub-phase 2, these signals transmit
transaction type information. These signals must connect the
appropriate pins/lands of all agents on the processor FSB. A[35:3]#
are source synchronous signals and are latched into the receiving
buffers by ADSTB[1:0]#.
On the active-to-inactive transition of RESET#, the processor samples
a subset of the A[35:3]# signals to determine power-on configuration.
See Section 6.1 for more details.
A20M# Input If A20M# (Address-20 Mask) is asserted, the processor masks
physical address bit 20 (A20#) before looking up a line in any internal
cache and before driving a read/write transaction on the bus.
Asserting A20M# emulates the 8086 processor's address wrap-around
at the 1-MB boundary. Assertion of A20M# is only supported in real
mode.
A20M# is an asynchronous signal. However, to ensure recognition of
this signal following an Input/Output write instruction, it must be valid
along with the TRDY# assertion of the corresponding Input/Output
Write bus transaction.
ADS# Input/Output ADS# (Address Strobe) is asserted to indicate the validity of the
transaction address on the A[35:3]# and REQ[4:0]# signals. All bus
agents observe the ADS# activation to begin protocol checking,
address decode, internal snoop, or deferred reply ID match operations
associated with the new transaction.
ADSTB[1:0]# Input/Output Address strobes are used to latch A[35:3]# and REQ[4:0]# on their
rising and falling edges. Strobes are associated with signals as shown
below.
BCLK[1:0] Input The differential pair BCLK (Bus Clock) determines the FSB frequency.
All processor FSB agents must receive these signals to drive their
outputs and latch their inputs.
All external timing parameters are specified with respect to the rising
edge of BCLK0 crossing V
CROSS
.
BNR# Input/Output BNR# (Block Next Request) is used to assert a bus stall by any bus
agent unable to accept new bus transactions. During a bus stall, the
current bus owner cannot issue any new transactions.
BPM[5:0]# Input/Output BPM[5:0]# (Breakpoint Monitor) are breakpoint and performance
monitor signals. They are outputs from the processor which indicate
the status of breakpoints and programmable counters used for
monitoring processor performance. BPM[5:0]# should connect the
appropriate pins/lands of all processor FSB agents.
BPM4# provides PRDY# (Probe Ready) functionality for the TAP port.
PRDY# is a processor output used by debug tools to determine
processor debug readiness.
BPM5# provides PREQ# (Probe Request) functionality for the TAP port.
PREQ# is used by debug tools to request debug operation of the
processor.
These signals do not have on-die termination.
BPRI# Input BPRI# (Bus Priority Request) is used to arbitrate for ownership of the
processor FSB. It must connect the appropriate pins/lands of all
processor FSB agents. Observing BPRI# active (as asserted by the
priority agent) causes all other agents to stop issuing new requests,
unless such requests are part of an ongoing locked operation. The
priority agent keeps BPRI# asserted until all of its requests are
completed, then releases the bus by de-asserting BPRI#.
Signals Associated Strobe
REQ[4:0]#, A[16:3]# ADSTB0#
A[35:17]# ADSTB1#
