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3000

Part # 3000
Description DUP RCPT PORTABLE OUTLET BX
Category LED
Availability Out of Stock
Qty 0
Qty Price
1 + $0.15000



Technical Document


DISCLAIMER: The information provided herein is solely for informational purposes. Customers must be aware of the suitability of this product for their application, and consider that variable factors such as Manufacturer, Product Category, Date Codes, Pictures and Descriptions may differ from available inventory.

Land Listing and Signal Descriptions
60 Dual-Core Intel® Xeon® Processor 3000 Series Datasheet
F15 D30# Source Synch Input/Output
F16 VSS Power/Other
F17 D37# Source Synch Input/Output
F18 D38# Source Synch Input/Output
F19 VSS Power/Other
F20 D41# Source Synch Input/Output
F21 D43# Source Synch Input/Output
F22 VSS Power/Other
F23 RESERVED
F24 TESTHI7 Power/Other Input
F25 TESTHI2 Power/Other Input
F26 TESTHI0 Power/Other Input
F27 VTT_SEL Power/Other Output
F28 BCLK0 Clock Input
F29 RESERVED
G1 FC27 Power/Other
G2 COMP2 Power/Other Input
G3 TESTHI8/FC42 Power/Other Input
G4 TESTHI9/FC43 Power/Other Input
G5 PECI Power/Other Input/Output
G6 RESERVED
G7 DEFER# Common Clock Input
G8 BPRI# Common Clock Input
G9 D16# Source Synch Input/Output
G10 FC38 Power/Other
G11 DBI1# Source Synch Input/Output
G12 DSTBN1# Source Synch Input/Output
G13 D27# Source Synch Input/Output
G14 D29# Source Synch Input/Output
G15 D31# Source Synch Input/Output
G16 D32# Source Synch Input/Output
G17 D36# Source Synch Input/Output
G18 D35# Source Synch Input/Output
G19 DSTBP2# Source Synch Input/Output
G20 DSTBN2# Source Synch Input/Output
G21 D44# Source Synch Input/Output
G22 D47# Source Synch Input/Output
G23 RESET# Common Clock Input
G24 TESTHI6 Power/Other Input
G25 TESTHI3 Power/Other Input
Table 4-2. Numerical Land Assignment
(Sheet 5 of 20)
Land
#
Land Name
Signal Buffer
Type
Direction
G26 TESTHI5 Power/Other Input
G27 TESTHI4 Power/Other Input
G28 BCLK1 Clock Input
G29 BSEL0 Power/Other Output
G30 BSEL2 Power/Other Output
H1 GTLREF0 Power/Other Input
H2 GTLREF1 Power/Other Input
H3 VSS Power/Other
H4 FC35 Power/Other
H5 TESTHI10 Power/Other Input
H6 VSS Power/Other
H7 VSS Power/Other
H8 VSS Power/Other
H9 VSS Power/Other
H10 VSS Power/Other
H11 VSS Power/Other
H12 VSS Power/Other
H13 VSS Power/Other
H14 VSS Power/Other
H15 FC32 Power/Other
H16 FC33 Power/Other
H17 VSS Power/Other
H18 VSS Power/Other
H19 VSS Power/Other
H20 VSS Power/Other
H21 VSS Power/Other
H22 VSS Power/Other
H23 VSS Power/Other
H24 VSS Power/Other
H25 VSS Power/Other
H26 VSS Power/Other
H27 VSS Power/Other
H28 VSS Power/Other
H29 FC15 Power/Other
H30 BSEL1 Power/Other Output
J1 VTT_OUT_LEFT Power/Other Output
J2 FC3 Power/Other
J3 FC22 Power/Other
J4 VSS Power/Other
J5 REQ1# Source Synch Input/Output
Table 4-2. Numerical Land Assignment
(Sheet 6 of 20)
Land
#
Land Name
Signal Buffer
Type
Direction
Land Listing and Signal Descriptions
Dual-Core Intel® Xeon® Processor 3000 Series Datasheet 61
J6 REQ4# Source Synch Input/Output
J7 VSS Power/Other
J8 VCC Power/Other
J9 VCC Power/Other
J10 VCC Power/Other
J11 VCC Power/Other
J12 VCC Power/Other
J13 VCC Power/Other
J14 VCC Power/Other
J15 VCC Power/Other
J16 FC31 Power/Other
J17 FC34 Power/Other
J18 VCC Power/Other
J19 VCC Power/Other
J20 VCC Power/Other
J21 VCC Power/Other
J22 VCC Power/Other
J23 VCC Power/Other
J24 VCC Power/Other
J25 VCC Power/Other
J26 VCC Power/Other
J27 VCC Power/Other
J28 VCC Power/Other
J29 VCC Power/Other
J30 VCC Power/Other
K1 LINT0 Asynch CMOS Input
K2 VSS Power/Other
K3 A20M# Asynch CMOS Input
K4 REQ0# Source Synch Input/Output
K5 VSS Power/Other
K6 REQ3# Source Synch Input/Output
K7 VSS Power/Other
K8 VCC Power/Other
K23 VCC Power/Other
K24 VCC Power/Other
K25 VCC Power/Other
K26 VCC Power/Other
K27 VCC Power/Other
K28 VCC Power/Other
K29 VCC Power/Other
Table 4-2. Numerical Land Assignment
(Sheet 7 of 20)
Land
#
Land Name
Signal Buffer
Type
Direction
K30 VCC Power/Other
L1 LINT1 Asynch CMOS Input
L2 TESTHI13 Power/Other Input
L3 VSS Power/Other
L4 A06# Source Synch Input/Output
L5 A03# Source Synch Input/Output
L6 VSS Power/Other
L7 VSS Power/Other
L8 VCC Power/Other
L23 VSS Power/Other
L24 VSS Power/Other
L25 VSS Power/Other
L26 VSS Power/Other
L27 VSS Power/Other
L28 VSS Power/Other
L29 VSS Power/Other
L30 VSS Power/Other
M1 VSS Power/Other
M2 THERMTRIP# Asynch CMOS Output
M3 STPCLK# Asynch CMOS Input
M4 A07# Source Synch Input/Output
M5 A05# Source Synch Input/Output
M6 REQ2# Source Synch Input/Output
M7 VSS Power/Other
M8 VCC Power/Other
M23 VCC Power/Other
M24 VCC Power/Other
M25 VCC Power/Other
M26 VCC Power/Other
M27 VCC Power/Other
M28 VCC Power/Other
M29 VCC Power/Other
M30 VCC Power/Other
N1 PWRGOOD Power/Other Input
N2 IGNNE# Asynch CMOS Input
N3 VSS Power/Other
N4 RESERVED
N5 RESERVED
N6 VSS Power/Other
N7 VSS Power/Other
Table 4-2. Numerical Land Assignment
(Sheet 8 of 20)
Land
#
Land Name
Signal Buffer
Type
Direction
Land Listing and Signal Descriptions
62 Dual-Core Intel® Xeon® Processor 3000 Series Datasheet
N8 VCC Power/Other
N23 VCC Power/Other
N24 VCC Power/Other
N25 VCC Power/Other
N26 VCC Power/Other
N27 VCC Power/Other
N28 VCC Power/Other
N29 VCC Power/Other
N30 VCC Power/Other
P1 TESTHI11 Power/Other Input
P2 SMI# Asynch CMOS Input
P3 INIT# Asynch CMOS Input
P4 VSS Power/Other
P5 RESERVED
P6 A04# Source Synch Input/Output
P7 VSS Power/Other
P8 VCC Power/Other
P23 VSS Power/Other
P24 VSS Power/Other
P25 VSS Power/Other
P26 VSS Power/Other
P27 VSS Power/Other
P28 VSS Power/Other
P29 VSS Power/Other
P30 VSS Power/Other
R1 COMP3 Power/Other Input
R2 VSS Power/Other
R3 FERR#/PBE# Asynch CMOS Output
R4 A08# Source Synch Input/Output
R5 VSS Power/Other
R6 ADSTB0# Source Synch Input/Output
R7 VSS Power/Other
R8 VCC Power/Other
R23 VSS Power/Other
R24 VSS Power/Other
R25 VSS Power/Other
R26 VSS Power/Other
R27 VSS Power/Other
R28 VSS Power/Other
R29 VSS Power/Other
Table 4-2. Numerical Land Assignment
(Sheet 9 of 20)
Land
#
Land Name
Signal Buffer
Type
Direction
R30 VSS Power/Other
T1 COMP1 Power/Other Input
T2 FC4 Power/Other
T3 VSS Power/Other
T4 A11# Source Synch Input/Output
T5 A09# Source Synch Input/Output
T6 VSS Power/Other
T7 VSS Power/Other
T8 VCC Power/Other
T23 VCC Power/Other
T24 VCC Power/Other
T25 VCC Power/Other
T26 VCC Power/Other
T27 VCC Power/Other
T28 VCC Power/Other
T29 VCC Power/Other
T30 VCC Power/Other
U1 FC28 Power/Other
U2 FC29 Power/Other
U3 FC30 Power/Other
U4 A13# Source Synch Input/Output
U5 A12# Source Synch Input/Output
U6 A10# Source Synch Input/Output
U7 VSS Power/Other
U8 VCC Power/Other
U23 VCC Power/Other
U24 VCC Power/Other
U25 VCC Power/Other
U26 VCC Power/Other
U27 VCC Power/Other
U28 VCC Power/Other
U29 VCC Power/Other
U30 VCC Power/Other
V1 MSID1 Power/Other Output
V2 RESERVED
V3 VSS Power/Other
V4 A15# Source Synch Input/Output
V5 A14# Source Synch Input/Output
V6 VSS Power/Other
V7 VSS Power/Other
Table 4-2. Numerical Land Assignment
(Sheet 10 of 20)
Land
#
Land Name
Signal Buffer
Type
Direction
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