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3000

Part # 3000
Description DUP RCPT PORTABLE OUTLET BX
Category LED
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Technical Document


DISCLAIMER: The information provided herein is solely for informational purposes. Customers must be aware of the suitability of this product for their application, and consider that variable factors such as Manufacturer, Product Category, Date Codes, Pictures and Descriptions may differ from available inventory.

Land Listing and Signal Descriptions
Dual-Core Intel® Xeon® Processor 3000 Series Datasheet 57
VSS R28 Power/Other
VSS R29 Power/Other
VSS R30 Power/Other
VSS R5 Power/Other
VSS R7 Power/Other
VSS T3 Power/Other
VSS T6 Power/Other
VSS T7 Power/Other
VSS U7 Power/Other
VSS V23 Power/Other
VSS V24 Power/Other
VSS V25 Power/Other
VSS V26 Power/Other
VSS V27 Power/Other
VSS V28 Power/Other
VSS V29 Power/Other
VSS V3 Power/Other
VSS V30 Power/Other
VSS V6 Power/Other
VSS V7 Power/Other
VSS W4 Power/Other
VSS W7 Power/Other
VSS Y2 Power/Other
VSS Y5 Power/Other
VSS Y7 Power/Other
VSS_MB_
REGULATION
AN6 Power/Other Output
VSS_SENSE AN4 Power/Other Output
VSSA B23 Power/Other
Table 4-1. Alphabetical Land
Assignments (Sheet 19 of 20)
Land Name Land #
Signal Buffer
Type
Direction
VTT A25 Power/Other
VTT A26 Power/Other
VTT A27 Power/Other
VTT A28 Power/Other
VTT A29 Power/Other
VTT A30 Power/Other
VTT B25 Power/Other
VTT B26 Power/Other
VTT B27 Power/Other
VTT B28 Power/Other
VTT B29 Power/Other
VTT B30 Power/Other
VTT C25 Power/Other
VTT C26 Power/Other
VTT C27 Power/Other
VTT C28 Power/Other
VTT C29 Power/Other
VTT C30 Power/Other
VTT D25 Power/Other
VTT D26 Power/Other
VTT D27 Power/Other
VTT D28 Power/Other
VTT D29 Power/Other
VTT D30 Power/Other
VTT_OUT_LEFT J1 Power/Other Output
VTT_OUT_RIGHT AA1 Power/Other Output
VTT_SEL F27 Power/Other Output
Table 4-1. Alphabetical Land
Assignments (Sheet 20 of 20)
Land Name Land #
Signal Buffer
Type
Direction
Land Listing and Signal Descriptions
58 Dual-Core Intel® Xeon® Processor 3000 Series Datasheet
Table 4-2. Numerical Land Assignment
(Sheet 1 of 20)
Land
#
Land Name
Signal Buffer
Type
Direction
A2 VSS Power/Other
A3 RS2# Common Clock Input
A4 D02# Source Synch Input/Output
A5 D04# Source Synch Input/Output
A6 VSS Power/Other
A7 D07# Source Synch Input/Output
A8 DBI0# Source Synch Input/Output
A9 VSS Power/Other
A10 D08# Source Synch Input/Output
A11 D09# Source Synch Input/Output
A12 VSS Power/Other
A13 COMP0 Power/Other Input
A14 D50# Source Synch Input/Output
A15 VSS Power/Other
A16 DSTBN3# Source Synch Input/Output
A17 D56# Source Synch Input/Output
A18 VSS Power/Other
A19 D61# Source Synch Input/Output
A20 RESERVED
A21 VSS Power/Other
A22 D62# Source Synch Input/Output
A23 VCCA Power/Other
A24 FC23 Power/Other
A25 VTT Power/Other
A26 VTT Power/Other
A27 VTT Power/Other
A28 VTT Power/Other
A29 VTT Power/Other
A30 VTT Power/Other
B1 VSS Power/Other
B2 DBSY# Common Clock Input/Output
B3 RS0# Common Clock Input
B4 D00# Source Synch Input/Output
B5 VSS Power/Other
B6 D05# Source Synch Input/Output
B7 D06# Source Synch Input/Output
B8 VSS Power/Other
B9 DSTBP0# Source Synch Input/Output
B10 D10# Source Synch Input/Output
B11 VSS Power/Other
B12 D13# Source Synch Input/Output
B13 COMP8 Power/Other Input
B14 VSS Power/Other
B15 D53# Source Synch Input/Output
B16 D55# Source Synch Input/Output
B17 VSS Power/Other
B18 D57# Source Synch Input/Output
B19 D60# Source Synch Input/Output
B20 VSS Power/Other
B21 D59# Source Synch Input/Output
B22 D63# Source Synch Input/Output
B23 VSSA Power/Other
B24 VSS Power/Other
B25 VTT Power/Other
B26 VTT Power/Other
B27 VTT Power/Other
B28 VTT Power/Other
B29 VTT Power/Other
B30 VTT Power/Other
C1 DRDY# Common Clock Input/Output
C2 BNR# Common Clock Input/Output
C3 LOCK# Common Clock Input/Output
C4 VSS Power/Other
C5 D01# Source Synch Input/Output
C6 D03# Source Synch Input/Output
C7 VSS Power/Other
C8 DSTBN0# Source Synch Input/Output
C9 FC38 Power/Other
C10 VSS Power/Other
C11 D11# Source Synch Input/Output
C12 D14# Source Synch Input/Output
C13 VSS Power/Other
C14 D52# Source Synch Input/Output
C15 D51# Source Synch Input/Output
C16 VSS Power/Other
C17 DSTBP3# Source Synch Input/Output
C18 D54# Source Synch Input/Output
C19 VSS Power/Other
C20 DBI3# Source Synch Input/Output
C21 D58# Source Synch Input/Output
Table 4-2. Numerical Land Assignment
(Sheet 2 of 20)
Land
#
Land Name
Signal Buffer
Type
Direction
Land Listing and Signal Descriptions
Dual-Core Intel® Xeon® Processor 3000 Series Datasheet 59
C22 VSS Power/Other
C23 VCCIOPLL Power/Other
C24 VSS Power/Other
C25 VTT Power/Other
C26 VTT Power/Other
C27 VTT Power/Other
C28 VTT Power/Other
C29 VTT Power/Other
C30 VTT Power/Other
D1 RESERVED
D2 ADS# Common Clock Input/Output
D3 VSS Power/Other
D4 HIT# Common Clock Input/Output
D5 VSS Power/Other
D6 VSS Power/Other
D7 D20# Source Synch Input/Output
D8 D12# Source Synch Input/Output
D9 VSS Power/Other
D10 D22# Source Synch Input/Output
D11 D15# Source Synch Input/Output
D12 VSS Power/Other
D13 D25# Source Synch Input/Output
D14 RESERVED
D15 VSS Power/Other
D16 RESERVED
D17 D49# Source Synch Input/Output
D18 VSS Power/Other
D19 DBI2# Source Synch Input/Output
D20 D48# Source Synch Input/Output
D21 VSS Power/Other
D22 D46# Source Synch Input/Output
D23 VCCPLL Power/Other
D24 VSS Power/Other
D25 VTT Power/Other
D26 VTT Power/Other
D27 VTT Power/Other
D28 VTT Power/Other
D29 VTT Power/Other
D30 VTT Power/Other
E2 VSS Power/Other
Table 4-2. Numerical Land Assignment
(Sheet 3 of 20)
Land
#
Land Name
Signal Buffer
Type
Direction
E3 TRDY# Common Clock Input
E4 HITM# Common Clock Input/Output
E5 FC20 Power/Other
E6 RESERVED
E7 RESERVED
E8 VSS Power/Other
E9 D19# Source Synch Input/Output
E10 D21# Source Synch Input/Output
E11 VSS Power/Other
E12 DSTBP1# Source Synch Input/Output
E13 D26# Source Synch Input/Output
E14 VSS Power/Other
E15 D33# Source Synch Input/Output
E16 D34# Source Synch Input/Output
E17 VSS Power/Other
E18 D39# Source Synch Input/Output
E19 D40# Source Synch Input/Output
E20 VSS Power/Other
E21 D42# Source Synch Input/Output
E22 D45# Source Synch Input/Output
E23 RESERVED
E24 FC10 Power/Other
E25 VSS Power/Other
E26 VSS Power/Other
E27 VSS Power/Other
E28 VSS Power/Other
E29 FC26 Power/Other
F2 FC5 Power/Other
F3 BR0# Common Clock Input/Output
F4 VSS Power/Other
F5 RS1# Common Clock Input
F6 FC21 Power/Other
F7 VSS Power/Other
F8 D17# Source Synch Input/Output
F9 D18# Source Synch Input/Output
F10 VSS Power/Other
F11 D23# Source Synch Input/Output
F12 D24# Source Synch Input/Output
F13 VSS Power/Other
F14 D28# Source Synch Input/Output
Table 4-2. Numerical Land Assignment
(Sheet 4 of 20)
Land
#
Land Name
Signal Buffer
Type
Direction
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