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Technical Document


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Document No. E1000E30 (Ver. 3.0)
Date Published February 2007 (K) Japan
Printed in Japan
URL: http://www.elpida.com
Elpida Memory, Inc. 2006-2007
PRELIMINARY DATA SHEET
1GB Fully Buffered DIMM
EBE11FD8AHFT
EBE11FD8AHFE
EBE11FD8AHFL
Specifications
Density: 1GB
Organization
128M words × 72 bits, 2 ranks
Mounting 18 pieces of 512M bits DDR2 SDRAM
sealed in FBGA
Package
240-pin fully buffered, socket type dual in line
memory module (FB-DIMM)
PCB height: 30.35mm
Lead pitch: 1.00mm
Advanced Memory Buffer (AMB): 655-ball FCBGA
Lead-free (RoHS compliant)
Power supply
DDR2 SDRAM: VDD = 1.8V ± 0.1V
AMB: VCC = 1.5V + 0.075V/0.045
Data rate: 667Mbps/533Mbps (max.)
Four internal banks for concurrent operation
(components)
Interface: SSTL_18
Burst lengths (BL): 4, 8
/CAS Latency (CL): 3, 4, 5
Precharge: auto precharge option for each burst
access
Refresh: auto-refresh, self-refresh
Refresh cycles: 8192 cycles/64ms
Average refresh period
7.8µs at 0°C TC +85°C
3.9µs at +85°C < TC +95°C
Operating case temperature range
TC = 0°C to +95°C
Features
JEDEC standard Raw Card B Design
Industry Standard Advanced Memory Buffer (AMB)
High-speed differential point-to-point link interface at
1.5V (JEDEC draft spec)
14 north-bound (NB) high speed serial lanes
10 south-bound (SB) high speed serial lanes
Various features/modes:
MemBIST and IBIST test functions
Transparent mode and direct access mode for
DRAM testing
Interface for a thermal sensor and status indicator
Channel error detection and reporting
Automatic DDR2 SDRAM bus and channel
calibration
SPD (serial presence detect) with 1piece of 256 byte
serial EEPROM
Note: Warranty void if removed DIMM heat
spreader.
Performance
FB-DIMM DDR2 SDRAM
System clock
frequency Speed grade
Peak channel
throughput FB-DIMM link data rate Speed Grade DDR data rate
167MHz PC2-5300F 8.0GByte/s 4.0Gbps DDR2-667 (5-5-5) 667Mbps
133MHz PC2-4200F 6.4GByte/s 3.2Gbps DDR2-533 (4-4-4) 533Mbps
EBE11FD8AHFT, EBE11FD8AHFE, EBE11FD8AHFL
Preliminary Data Sheet E1000E30 (Ver. 3.0)
2
Ordering Information
Part number
DIMM speed
grade
Component JEDEC
speed bin (CL-tRCD-tRP)
Mounted devices*
1
Mounted AMB*
2
EBE11FD8AHFT-6E-E PC2-5300F DDR2-667 (5-5-5) EDE5108AHSE-6E-E IDT Rev. C1
EBE11FD8AHFT-5C-E PC2-4200F DDR2-533 (4-4-4)
EDE5108AHSE-6E-E
EDE5108AHSE-5C-E
EBE11FD8AHFE-6E-E PC2-5300F DDR2-667 (5-5-5) EDE5108AHSE-6E-E NECEL Rev. B5+
EBE11FD8AHFE-5C-E PC2-4200F DDR2-533 (4-4-4)
EDE5108AHSE-6E-E
EDE5108AHSE-5C-E
EBE11FD8AHFL-6E-E PC2-5300F DDR2-667 (5-5-5) EDE5108AHSE-6E-E INTEL Rev. D1
EBE11FD8AHFL-5C-E PC2-4200F DDR2-533 (4-4-4)
EDE5108AHSE-6E-E
EDE5108AHSE-5C-E
Notes: 1. Please refer to the EDE5108AHSE, EDE5116AHSE datasheet (E0908E) for detailed operation part and
timing waveforms.
2. Please refer to the following documents for detailed operation part and timing waveforms.
Advanced Memory Buffer (AMB) specification
FB-DIMM Architecture and Protocol specification
Part Number
Elpida Memory
Density / Rank
11: 1GB/2-rank
Module Type
F: Fully Buffered
Mono Density
D: 512Mbit
Die Rev. (Mono)
DRAM Speed Grade
6E: DDR2-667 (5-5-5)
5C: DDR2-533 (4-4-4)
Product Family
E: DDR2
Type
B: Module
Power Supply, Interface
A: 1.8V, SSTL_1.8
Module Outline
F: 240-pin DIMM
AMB Device Information
T: IDT, Rev.C1
E: NECEL, Rev.B5+
L: Intel, Rev.D1
Mono Organization
8: x8
E B E 11 F D 8 A H F T - 6E - E
Environment code
E: Lead Free
(RoHS compliant)
EBE11FD8AHFT, EBE11FD8AHFE, EBE11FD8AHFL
Preliminary Data Sheet E1000E30 (Ver. 3.0)
3
Advanced Memory Buffer Overview
The Advanced Memory Buffer (AMB) reference design complies with the FB-DIMM Architecture and Protocol
Specification. It supports DDR2 SDRAM main memory. The AMB allows buffering of memory traffic to support large
memory capacities. All memory control for the DRAM resides in the host, including memory request initiation, timing,
refresh, scrubbing, sparing, configuration access, and power management. The AMB interface is responsible for
handling FB-DIMM channel and memory requests to and from the local DIMM and for forwarding requests to other
DIMMs on the FB-DIMM channel.
The FB-DIMM provides a high memory bandwidth, large capacity channel solution that has a narrow host interface.
FB-DIMMs use commodity DRAMs isolated from the channel behind a buffer on the DIMM. The memory capacity is
288 devices per channel and total memory capacity scales with DRAM bit density.
The AMB is the buffer that isolates the DRAMs from the channel.
Advanced Memory Buffer Functionality
The AMB will perform the following FB-DIMM channel functions.
Supports channel initialization procedures as defined in the initialization chapter of the FB-DIMM Architecture and
Protocol Specification to align the clocks and the frame boundaries, verify channel connectivity, and identify AMB
DIMM position.
Supports the forwarding of southbound and northbound frames, servicing requests directed to a specific AMB or
DIMM, as defined in the protocol chapter, and merging the return data into the northbound frames.
If the AMB resides on the last DIMM in the channel, the AMB initializes northbound frames.
Detects errors on the channel and reports them to the host memory controller.
Support the FB-DIMM configuration register set as defined in the register chapters.
Acts as DRAM memory buffer for all read, write, and configuration accesses addressed to the DIMM.
Provides a read buffer FIFO and a write buffer FIFO.
Supports an SMBus protocol interface for access to the AMB configuration registers.
Provides logic to support MemBIST and IBIST design for test functions.
Provides a register interface for the thermal sensor and status indicator.
Functions as a repeater to extend the maximum length of FB-DIMM links.
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