Serial Communications Interface (SCI)

I/O Registers

MC68HC908AZ60A — Rev 2.0 Technical Data

MOTOROLA Serial Communications Interface (SCI) 277

NF — Receiver Noise Flag Bit

This clearable, read-only bit is set when the SCI detects noise on the

RxD pin. NF generates an NF CPU interrupt request if the NEIE bit in

SCC3 is also set. Clear the NF bit by reading SCS1 and then reading

the SCDR. Reset clears the NF bit.

1 = Noise detected

0 = No noise detected

FE — Receiver Framing Error Bit

This clearable, read-only bit is set when a logic 0 is accepted as the

stop bit. FE generates an SCI error CPU interrupt request if the FEIE

bit in SCC3 also is set. Clear the FE bit by reading SCS1 with FE set

and then reading the SCDR. Reset clears the FE bit.

1 = Framing error detected

0 = No framing error detected

PE — Receiver Parity Error Bit

This clearable, read-only bit is set when the SCI detects a parity error

in incoming data. PE generates a PE CPU interrupt request if the

PEIE bit in SCC3 is also set. Clear the PE bit by reading SCS1 with

PE set and then reading the SCDR. Reset clears the PE bit.

1 = Parity error detected

0 = No parity error detected

Serial Communications Interface (SCI)

Technical Data MC68HC908AZ60A — Rev 2.0

278 Serial Communications Interface (SCI) MOTOROLA

18.9.5 SCI Status Register 2

SCI status register 2 contains flags to signal the following conditions:

• Break character detected

• Incoming data

BKF — Break Flag Bit

This clearable, read-only bit is set when the SCI detects a break

character on the RxD pin. In SCS1, the FE and SCRF bits are also

set. In 9-bit character transmissions, the R8 bit in SCC3 is cleared.

BKF does not generate a CPU interrupt request. Clear BKF by

reading SCS2 with BKF set and then reading the SCDR. Once

cleared, BKF can become set again only after logic 1s again appear

on the RxD pin followed by another break character. Reset clears the

BKF bit.

1 = Break character detected

0 = No break character detected

RPF — Reception in Progress Flag Bit

This read-only bit is set when the receiver detects a logic 0 during the

RT1 time period of the start bit search. RPF does not generate an

interrupt request. RPF is reset after the receiver detects false start bits

(usually from noise or a baud rate mismatch), or when the receiver

detects an idle character. Polling RPF before disabling the SCI

module or entering stop mode can show whether a reception is in

progress.

1 = Reception in progress

0 = No reception in progress

Address: $0017

Bit 7654321Bit 0

Read: 000000BKFRPF

Write:

Reset:00000000

= Unimplemented

Figure 18-16. SCI Status Register 2 (SCS2)

Serial Communications Interface (SCI)

I/O Registers

MC68HC908AZ60A — Rev 2.0 Technical Data

MOTOROLA Serial Communications Interface (SCI) 279

18.9.6 SCI Data Register

The SCI data register is the buffer between the internal data bus and the

receive and transmit shift registers. Reset has no effect on data in the

SCI data register.

R7/T7:R0/T0 — Receive/Transmit Data Bits

Reading address $0018 accesses the read-only received data bits,

R7:R0. Writing to address $0018 writes the data to be transmitted,

T7:T0. Reset has no effect on the SCI data register.

NOTE: Do not use read-modify-write instructions on the SCI data register.

18.9.7 SCI Baud Rate Register

The baud rate register selects the baud rate for both the receiver and the

transmitter.

Address: $0018

Bit 7654321Bit 0

Read: R7 R6 R5 R4 R3 R2 R1 R0

Write: T7 T6 T5 T4 T3 T2 T1 T0

Reset: Unaffected by Reset

Figure 18-17. SCI Data Register (SCDR)

Address: $0019

Bit 7654321Bit 0

SCP1 SCP0 R SCR2 SCR1 SCR0

Write:

Reset:00000000

= Unimplemented R = Reserved

Figure 18-18. SCI Baud Rate Register (SCBR)

Part #	8A/S6
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8A/S6

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