Serial Communications Interface (SCI)

Technical Data MC68HC908AZ60A — Rev 2.0

274 Serial Communications Interface (SCI) MOTOROLA

18.9.4 SCI Status Register 1

SCI status register 1 contains flags to signal the following conditions:

• Transfer of SCDR data to transmit shift register complete

• Transmission complete

• Transfer of receive shift register data to SCDR complete

• Receiver input idle

• Receiver overrun

• Noisy data

• Framing error

• Parity error

SCTE — SCI Transmitter Empty Bit

This clearable, read-only bit is set when the SCDR transfers a

character to the transmit shift register. SCTE can generate an SCI

transmitter CPU interrupt request. When the SCTIE bit in SCC2 is set,

SCTE generates an SCI transmitter CPU interrupt request. In normal

operation, clear the SCTE bit by reading SCS1 with SCTE set and

then writing to SCDR. Reset sets the SCTE bit.

1 = SCDR data transferred to transmit shift register

0 = SCDR data not transferred to transmit shift register

Address: $0016

Bit 7654321Bit 0

Read: SCTE TC SCRF IDLE OR NF FE PE

Write:

Reset:11000000

= Unimplemented

Figure 18-14. SCI Status Register 1 (SCS1)

Serial Communications Interface (SCI)

I/O Registers

MC68HC908AZ60A — Rev 2.0 Technical Data

MOTOROLA Serial Communications Interface (SCI) 275

TC — Transmission Complete Bit

This read-only bit is set when the SCTE bit is set, and no data,

preamble, or break character is being transmitted. TC generates an

SCI transmitter CPU interrupt request if the TCIE bit in SCC2 is also

set. TC is cleared automatically when data, preamble, or break is

queued and ready to be sent. There may be up to 1.5 transmitter

clocks of latency between queueing data, preamble, and break and

the transmission actually starting. Reset sets the TC bit.

1 = No transmission in progress

0 = Transmission in progress

SCRF — SCI Receiver Full Bit

This clearable, read-only bit is set when the data in the receive shift

receiver CPU interrupt request. When the SCRIE bit in SCC2 is set

the SCRF generates a CPU interrupt request. In normal operation,

clear the SCRF bit by reading SCS1 with SCRF set and then reading

the SCDR. Reset clears SCRF.

1 = Received data available in SCDR

0 = Data not available in SCDR

IDLE — Receiver Idle Bit

This clearable, read-only bit is set when 10 or 11 consecutive logic 1s

appear on the receiver input. IDLE generates an SCI error CPU

interrupt request if the ILIE bit in SCC2 is also set. Clear the IDLE bit

by reading SCS1 with IDLE set and then reading the SCDR. After the

receiver is enabled, it must receive a valid character that sets the

SCRF bit before an idle condition can set the IDLE bit. Also, after the

IDLE bit has been cleared, a valid character must again set the SCRF

bit before an idle condition can set the IDLE bit. Reset clears the IDLE

bit.

1 = Receiver input idle

0 = Receiver input active (or idle since the IDLE bit was cleared)

OR — Receiver Overrun Bit

This clearable, read-only bit is set when software fails to read the

SCDR before the receive shift register receives the next character.

The OR bit generates an SCI error CPU interrupt request if the ORIE

Serial Communications Interface (SCI)

Technical Data MC68HC908AZ60A — Rev 2.0

276 Serial Communications Interface (SCI) MOTOROLA

bit in SCC3 is also set. The data in the shift register is lost, but the data

already in the SCDR is not affected. Clear the OR bit by reading SCS1

with OR set and then reading the SCDR. Reset clears the OR bit.

1 = Receive shift register full and SCRF = 1

0 = No receiver overrun

Software latency may allow an overrun to occur between reads of SCS1

and SCDR in the flag-clearing sequence. Figure 18-15 shows the

normal flag-clearing sequence and an example of an overrun caused by

a delayed flag-clearing sequence. The delayed read of SCDR does not

clear the OR bit because OR was not set when SCS1 was read. Byte 2

caused the overrun and is lost. The next flag-clearing sequence reads

byte 3 in the SCDR instead of byte 2.

In applications that are subject to software latency or in which it is

important to know which byte is lost due to an overrun, the flag-clearing

routine can check the OR bit in a second read of SCS1 after reading the

data register.

Figure 18-15. Flag Clearing Sequence

BYTE 1

NORMAL FLAG CLEARING SEQUENCE

READ SCS1

SCRF = 1

READ SCDR

BYTE 1

SCRF = 1

BYTE 2 BYTE 3 BYTE 4

OR = 0

READ SCS1

SCRF = 1

OR = 0

READ SCDR

BYTE 2

SCRF = 0

READ SCS1

SCRF = 1

OR = 0

SCRF = 1

SCRF = 0

READ SCDR

BYTE 3

SCRF = 0

BYTE 1

READ SCS1

SCRF = 1

READ SCDR

BYTE 1

SCRF = 1

BYTE 2 BYTE 3 BYTE 4

OR = 0

READ SCS1

SCRF = 1

OR = 1

READ SCDR

BYTE 3

DELAYED FLAG CLEARING SEQUENCE

OR = 1

SCRF = 1

OR = 1

SCRF = 0

OR = 1

SCRF = 0

OR = 0

Part #	8A/S6
Description	Incandescent S Light Lamp
Category	LAMP
Availability	In Stock
Qty	2

8A/S6

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