Serial Communications Interface (SCI)

I/O Registers

MC68HC908AZ60A — Rev 2.0 Technical Data

MOTOROLA Serial Communications Interface (SCI) 271

RE — Receiver Enable Bit

Setting this read/write bit enables the receiver. Clearing the RE bit

disables the receiver but does not affect receiver interrupt flag bits.

Reset clears the RE bit.

1 = Receiver enabled

0 = Receiver disabled

NOTE: Writing to the RE bit is not allowed when the enable SCI bit (ENSCI) is

clear. ENSCI is in SCI control register 1.

RWU — Receiver Wakeup Bit

This read/write bit puts the receiver in a standby state during which

receiver interrupts are disabled. The WAKE bit in SCC1 determines

whether an idle input or an address mark brings the receiver out of the

standby state and clears the RWU bit. Reset clears the RWU bit.

1 = Standby state

0 = Normal operation

SBK — Send Break Bit

Setting and then clearing this read/write bit transmits a break

character followed by a logic 1. The logic 1 after the break character

guarantees recognition of a valid start bit. If SBK remains set, the

transmitter continuously transmits break characters with no logic 1s

between them. Reset clears the SBK bit.

1 = Transmit break characters

0 = No break characters being transmitted

NOTE: Do not toggle the SBK bit immediately after setting the SCTE bit.

Toggling SBK before the preamble begins causes the SCI to send a

break character instead of a preamble.

Serial Communications Interface (SCI)

Technical Data MC68HC908AZ60A — Rev 2.0

272 Serial Communications Interface (SCI) MOTOROLA

18.9.3 SCI Control Register 3

SCI control register 3:

• Stores the ninth SCI data bit received and the ninth SCI data bit to

be transmitted.

• Enables the following interrupts:

– Receiver overrun interrupts

– Noise error interrupts

– Framing error interrupts

– Parity error interrupts

R8 — Received Bit 8

When the SCI is receiving 9-bit characters, R8 is the read-only ninth

bit (bit 8) of the received character. R8 is received at the same time

that the SCDR receives the other 8 bits.

When the SCI is receiving 8-bit characters, R8 is a copy of the eighth

bit (bit 7). Reset has no effect on the R8 bit.

T8 — Transmitted Bit 8

When the SCI is transmitting 9-bit characters, T8 is the read/write

ninth bit (bit 8) of the transmitted character. T8 is loaded into the

transmit shift register at the same time that the SCDR is loaded into

the transmit shift register. Reset has no effect on the T8 bit.

Address: $0015

Bit 7654321Bit 0

Read: R8

T8 R R ORIE NEIE FEIE PEIE

Write:

Reset:UU000000

= Unimplemented R = Reserved U = Unaffected

Figure 18-13. SCI Control Register 3 (SCC3)

Serial Communications Interface (SCI)

I/O Registers

MC68HC908AZ60A — Rev 2.0 Technical Data

MOTOROLA Serial Communications Interface (SCI) 273

ORIE — Receiver Overrun Interrupt Enable Bit

This read/write bit enables SCI error CPU interrupt requests

generated by the receiver overrun bit, OR.

1 = SCI error CPU interrupt requests from OR bit enabled

0 = SCI error CPU interrupt requests from OR bit disabled

NEIE — Receiver Noise Error Interrupt Enable Bit

This read/write bit enables SCI error CPU interrupt requests

generated by the noise error bit, NE. Reset clears NEIE.

1 = SCI error CPU interrupt requests from NE bit enabled

0 = SCI error CPU interrupt requests from NE bit disabled

FEIE — Receiver Framing Error Interrupt Enable Bit

This read/write bit enables SCI error CPU interrupt requests

generated by the framing error bit, FE. Reset clears FEIE.

1 = SCI error CPU interrupt requests from FE bit enabled

0 = SCI error CPU interrupt requests from FE bit disabled

PEIE — Receiver Parity Error Interrupt Enable Bit

This read/write bit enables SCI receiver CPU interrupt requests

generated by the parity error bit, PE. Reset clears PEIE.

1 = SCI error CPU interrupt requests from PE bit enabled

0 = SCI error CPU interrupt requests from PE bit disabled

Part #	8A/S6
Description	Incandescent S Light Lamp
Category	LAMP
Availability	In Stock
Qty	2

8A/S6

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