Serial Communications Interface (SCI)

Technical Data MC68HC908AZ60A — Rev 2.0

268 Serial Communications Interface (SCI) MOTOROLA

PTY — Parity Bit

This read/write bit determines whether the SCI generates and checks

for odd parity or even parity. (See Table 18-8). Reset clears the PTY

bit.

1 = Odd parity

0 = Even parity

NOTE: Changing the PTY bit in the middle of a transmission or reception can

generate a parity error.

18.9.2 SCI Control Register 2

SCI control register 2:

• Enables the following CPU interrupt requests:

– Enables the SCTE bit to generate transmitter CPU interrupt

requests

– Enables the TC bit to generate transmitter CPU interrupt

requests

– Enables the SCRF bit to generate receiver CPU interrupt

requests

– Enables the IDLE bit to generate receiver CPU interrupt

requests

Table 18-8. Character Format Selection

Control Bits Character Format

MPEN:PTY

Start

Bits

Data

Bits

Parity

Stop

Bits

Character

Length

0 0X 1 8 None 1 10 Bits

1 0X 1 9 None 1 11 Bits

0 10 1 7 Even 1 10 Bits

011 17Odd110 Bits

1 10 1 8 Even 1 11 Bits

111 18Odd111 Bits

Serial Communications Interface (SCI)

I/O Registers

MC68HC908AZ60A — Rev 2.0 Technical Data

MOTOROLA Serial Communications Interface (SCI) 269

• Enables the transmitter

• Enables the receiver

• Enables SCI wakeup

• Transmits SCI break characters

SCTIE — SCI Transmit Interrupt Enable Bit

This read/write bit enables the SCTE bit to generate SCI transmitter

CPU interrupt requests. Setting the SCTIE bit in SCC3 enables the

SCTE bit to generate CPU interrupt requests. Reset clears the SCTIE

bit.

1 = SCTE enabled to generate CPU interrupt

0 = SCTE not enabled to generate CPU interrupt

TCIE — Transmission Complete Interrupt Enable Bit

This read/write bit enables the TC bit to generate SCI transmitter CPU

interrupt requests. Reset clears the TCIE bit.

1 = TC enabled to generate CPU interrupt requests

0 = TC not enabled to generate CPU interrupt requests

Address: $0014

Bit 7654321Bit 0

Read:

SCTIE TCIE SCRIE ILIE TE RE RWU SBK

Write:

Reset:00000000

Figure 18-12. SCI Control Register 2 (SCC2)

Serial Communications Interface (SCI)

Technical Data MC68HC908AZ60A — Rev 2.0

270 Serial Communications Interface (SCI) MOTOROLA

SCRIE — SCI Receive Interrupt Enable Bit

This read/write bit enables the SCRF bit to generate SCI receiver

CPU interrupt requests. Setting the SCRIE bit in SCC3 enables the

SCRF bit to generate CPU interrupt requests. Reset clears the SCRIE

bit.

1 = SCRF enabled to generate CPU interrupt

0 = SCRF not enabled to generate CPU interrupt

ILIE — Idle Line Interrupt Enable Bit

This read/write bit enables the IDLE bit to generate SCI receiver CPU

interrupt requests. Reset clears the ILIE bit.

1 = IDLE enabled to generate CPU interrupt requests

0 = IDLE not enabled to generate CPU interrupt requests

TE — Transmitter Enable Bit

Setting this read/write bit begins the transmission by sending a

preamble of 10 or 11 logic 1s from the transmit shift register to the

TxD pin. If software clears the TE bit, the transmitter completes any

transmission in progress before the TxD returns to the idle condition

(logic 1). Clearing and then setting TE during a transmission queues

an idle character to be sent after the character currently being

transmitted. Reset clears the TE bit.

1 = Transmitter enabled

0 = Transmitter disabled

NOTE: Writing to the TE bit is not allowed when the enable SCI bit (ENSCI) is

clear. ENSCI is in SCI control register 1.

Part #	8A/S6
Description	Incandescent S Light Lamp
Category	LAMP
Availability	In Stock
Qty	2

8A/S6

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