Low Voltage Inhibit (LVI)
Technical Data MC68HC908AZ60A — Rev 2.0
232 Low Voltage Inhibit (LVI) MOTOROLA
16.4.1 Polled LVI Operation
In applications that can operate at V
DD
levels below the LVI
TRIPF
level,
software can monitor V
DD
by polling the LVIOUT bit. In the configuration
register, the LVIPWR bit must be at logic 1 to enable the LVI module, and
the LVIRST bit must be at logic 0 to disable LVI resets.
16.4.2 Forced Reset Operation
In applications that require V
DD
to remain above the LVI
TRIPF
level,
enabling LVI resets allows the LVI module to reset the MCU when V
DD
falls to the LVI
TRIPF
level and remains at or below that level for nine or
more consecutive CPU cycles. In the configuration register, the LVIPWR
and LVIRST bits must be at logic 1 to enable the LVI module and to
enable LVI resets.
16.4.3 False Reset Protection
The V
DD
pin level is digitally filtered to reduce false resets due to power
supply noise. In order for the LVI module to reset the MCU,V
DD
must
remain at or below the LVI
TRIPF
level for nine or more consecutive CPU
cycles. V
DD
must be above LVI
TRIPR
for only one CPU cycle to bring the
MCU out of reset.
Figure 16-2. LVI I/O Register Summary
Addr. Register Name Bit 7654321Bit 0
$FE0F LVI Status Register (LVISR) LVIOUT
= Unimplemented
