Low Voltage Inhibit (LVI)
Technical Data MC68HC908AZ60A — Rev 2.0
230 Low Voltage Inhibit (LVI) MOTOROLA
NOTE: If a low voltage interrupt (LVI) occurs during programming of EEPROM
or Flash memory, then adequate programming time may not have been
allowed to ensure the integrity and retention of the data. It is the
responsibility of the user to ensure that in the event of an LVI any
addresses being programmed receive specification programming
conditions.
16.4 Functional Description
Figure 16-1 shows the structure of the LVI module. The LVI is enabled
out of reset. The LVI module contains a bandgap reference circuit and
comparator. The LVI power bit, LVIPWR, enables the LVI to monitor V
DD
voltage. The LVI reset bit, LVIRST, enables the LVI module to generate
a reset when V
DD
falls below a voltage, LVI
TRIPF
, and remains at or
below that level for nine or more consecutive CPU cycles.
Note that short V
DD
spikes may not trip the LVI. It is the user’s
responsibility to ensure a clean V
DD
signal within the specified operating
voltage range if normal microcontroller operation is to be guaranteed.
LVISTOP, enables the LVI module during stop mode. This will ensure
when the STOP instruction is implemented, the LVI will continue to
monitor the voltage level on V
DD
. LVIPWR, LVISTOP, and LVIRST are
in the configuration register, CONFIG-1 (see Configuration Register
(CONFIG-1) on page 197).
Once an LVI reset occurs, the MCU remains in reset until V
DD
rises
above a voltage, LVI
TRIPR
. V
DD
must be above LVI
TRIPR
for only one
CPU cycle to bring the MCU out of reset (see Forced Reset Operation
on page 232). The output of the comparator controls the state of the
LVIOUT flag in the LVI status register (LVISR).
An LVI reset also drives the RST pin low to provide low-voltage
protection to external peripheral devices.
