Monitor ROM (MON)
Technical Data MC68HC908AZ60A — Rev 2.0
212 Monitor ROM (MON) MOTOROLA
14.4.1 Entering Monitor Mode
Table 14-1 shows the pin conditions for entering monitor mode.
Enter monitor mode by either
• Executing a software interrupt instruction (SWI) or
• Applying a logic 0 and then a logic 1 to the RST
pin.
Once out of reset, the MCU waits for the host to send eight security bytes
(see Security on page 220). After the security bytes, the MCU sends a
break signal (10 consecutive logic 0s) to the host computer, indicating
that it is ready to receive a command.
Monitor mode uses alternate vectors for reset, SWI, and break interrupt.
The alternate vectors are in the $FE page instead of the $FF page and
allow code execution from the internal monitor firmware instead of user
code. The COP module is disabled in monitor mode as long as V
HI
(see
5.0 Volt DC Electrical Characteristics on page 532), is applied to
either the IRQ pin or the RESET pin. (See System Integration Module
(SIM) on page 147 for more information on modes of operation).
NOTE: Holding the PTC3 pin low when entering monitor mode causes a bypass
of a divide-by-two stage at the oscillator. The CGMOUT frequency is
equal to the CGMXCLK frequency, and the OSC1 input directly
generates internal bus clocks. In this case, the OSC1 signal must have
a 50% duty cycle at maximum bus frequency.
Table 14-1. Mode Selection
IRQ Pin
PTC0 Pin
PTC1 Pin
PTA0 Pin
PTC3 Pin
Mode CGMOUT
Bus
Frequency
V
HI
(1)
1011Monitor or
V
HI
(1)
1010Monitor CGMXCLK
1. For V
HI
, 5.0 Volt DC Electrical Characteristics on page 532, and Maximum Ratings on
page 530.
CGMXCLK
2
-----------------------------
CGMVCLK
2
-----------------------------
CGMOUT
2
--------------------------
CGMOUT
2
--------------------------
