Break Module (BRK)
Technical Data MC68HC908AZ60A — Rev 2.0
206 Break Module (BRK) MOTOROLA
13.4.2 CPU During Break Interrupts
The CPU starts a break interrupt by:
• Loading the instruction register with the SWI instruction
• Loading the program counter with $FFFC:$FFFD ($FEFC:$FEFD
in monitor mode)
The break interrupt begins after completion of the CPU instruction in
progress. If the break address register match occurs on the last cycle of
a CPU instruction, the break interrupt begins immediately.
13.4.3 TIM During Break Interrupts
A break interrupt stops the timer counter.
13.4.4 COP During Break Interrupts
The COP is disabled during a break interrupt when V
Hi
is present on the
RST
pin.
13.5 Low-Power Modes
The WAIT and STOP instructions put the MCU in low power-consump-
tion standby modes.
13.5.1 Wait Mode
If enabled, the break module is active in wait mode. The SIM break wait
bit (BW) in the SIM break status register indicates whether wait was
exited by a break interrupt. If so, the user can modify the return address
on the stack by subtracting one from it. (See SIM Break Status Register
on page 166).
