Configuration Register (CONFIG-2)

Technical Data MC68HC908AZ60A — Rev 2.0

202 Configuration Register (CONFIG-2) MOTOROLA

AT60A — Device indicator

This read-only bit is used to distinguish an MC68HC908AS60A and

MC68HC908AZ60A from older non-’A’ suffix versions.

1 = ‘A’ version

0 = Non-’A’ version

EEDIVCLK — EEPROM Timebase Divider Clock select bit

This bit selects the reference clock source for the EEPROM-1 and

EEPROM-2 timebase divider modules.

1 = EExDIV clock input is driven by internal bus clock

0 = EExDIV clock input is driven by CGMXCLK

MSCAND — MSCAN Disable Bit

MSCAND disables the MSCAN module. (See MSCAN Controller

(MSCAN08) on page 379).

1 = MSCAN module disabled

0 = MSCAN Module enabled

AZxx — AZxx Emulator Enable Bit

AZxx enables the MC68HC08AZxx emulator configuration. This bit

will be 0 out of reset.

1 = MC68HC08AZxx emulator enabled

0 = MC68HC08ASxx emulator enabled

NOTE: AZxx bit is reset by a POWER-ON-RESET only.

MC68HC908AZ60A — Rev 2.0 Technical Data

MOTOROLA Break Module (BRK) 203

Technical Data — MC68HC908AZ60A

Section 13. Break Module (BRK)

13.1 Contents

13.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .203

13.3 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .203

13.4 Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . .204

13.4.1 Flag Protection During Break Interrupts . . . . . . . . . . . .205

13.4.2 CPU During Break Interrupts . . . . . . . . . . . . . . . . . . . . .206

13.4.3 TIM During Break Interrupts . . . . . . . . . . . . . . . . . . . . . .206

13.4.4 COP During Break Interrupts . . . . . . . . . . . . . . . . . . . . .206

13.5 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .206

13.5.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .206

13.5.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .207

13.6 Break Module Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . .207

13.6.1 Break Status and Control Register. . . . . . . . . . . . . . . . .207

13.6.2 Break Address Registers. . . . . . . . . . . . . . . . . . . . . . . . .208

13.2 Introduction

The break module can generate a break interrupt that stops normal

program flow at a defined address to enter a background program.

13.3 Features

• Accessible I/O Registers during Break Interrupts

• CPU-Generated Break Interrupts

• Software-Generated Break Interrupts

• COP Disabling during Break Interrupts

Break Module (BRK)

Technical Data MC68HC908AZ60A — Rev 2.0

204 Break Module (BRK) MOTOROLA

13.4 Functional Description

When the internal address bus matches the value written in the break

address registers, the break module issues a breakpoint signal to the

CPU. The CPU then loads the instruction register with a software

interrupt instruction (SWI) after completion of the current CPU

instruction. The program counter vectors to $FFFC and $FFFD ($FEFC

and $FEFD in monitor mode).

The following events can cause a break interrupt to occur:

• A CPU-generated address (the address in the program counter)

matches the contents of the break address registers.

• Software writes a logic 1 to the BRKA bit in the break status and

control register.

When a CPU-generated address matches the contents of the break

address registers, the break interrupt begins after the CPU completes its

current instruction. A return-from-interrupt instruction (RTI) in the break

routine ends the break interrupt and returns the MCU to normal

operation. Figure 13-1 shows the structure of the break module.

Figure 13-1. Break Module Block Diagram

IAB[15:8]

IAB[7:0]

8-BIT COMPARATOR

CONTROL

BREAK ADDRESS REGISTER LOW

BREAK ADDRESS REGISTER HIGH

IAB[15:0]

BREAK

Part #	8A/S6
Description	Incandescent S Light Lamp
Category	LAMP
Availability	In Stock
Qty	2

8A/S6

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Technical Document