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8A/S6

Part # 8A/S6
Description Incandescent S Light Lamp
Category LAMP
Availability In Stock
Qty 2
Qty Price
1 + $2.43518
Manufacturer Available Qty
General Electric
  • Shipping Freelance Stock: 2
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Technical Document


DISCLAIMER: The information provided herein is solely for informational purposes. Customers must be aware of the suitability of this product for their application, and consider that variable factors such as Manufacturer, Product Category, Date Codes, Pictures and Descriptions may differ from available inventory.

MC68HC908AZ60A — Rev 2.0 Technical Data
MOTOROLA List of Figures 19
Technical Data — MC68HC908AZ60A
List of Figures
Figure Title Page
1-1 MCU Block Diagram for the MC68HC908AZ60A (64-Pin QFP)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
1-2 MCU Block Diagram for the MC68HC908AS60A (64-Pin QFP
and 52-pin PLCC). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
1-3 MC68HC908AZ60A (64-Pin QFP) . . . . . . . . . . . . . . . . . . . . . .37
1-4 MC68HC908AS60A (64-Pin QFP) . . . . . . . . . . . . . . . . . . . . . .38
1-5 MC68HC908AS60A (52-Pin PLCC) . . . . . . . . . . . . . . . . . . . . .39
1-6 Power supply bypassing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
2-1 Memory Map (Continued). . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
2-2 I/O Data, Status and Control Registers . . . . . . . . . . . . . . . . . .54
2-3 Additional Status and Control Registers. . . . . . . . . . . . . . . . . .59
4-1 FLASH-1 Control Register (FL1CR) . . . . . . . . . . . . . . . . . . . . .67
4-2 FLASH-1 Block Protect Register (FL1BPR) . . . . . . . . . . . . . . .68
4-3 FLASH-1 Block Protect Start Address . . . . . . . . . . . . . . . . . . .69
4-4 FLASH Programming Algorithm Flowchart. . . . . . . . . . . . . . . .75
5-1 FLASH-2 Control Register (FL2CR) . . . . . . . . . . . . . . . . . . . . .79
5-2 FLASH-2 Block Protect Register (FL2BPR) . . . . . . . . . . . . . . .80
5-3 FLASH-2 Block Protect Start Address . . . . . . . . . . . . . . . . . . .81
5-4 FLASH Programming Algorithm Flowchart. . . . . . . . . . . . . . . .87
6-1 EEPROM-1 Register Summary . . . . . . . . . . . . . . . . . . . . . . . .91
6-2 EEPROM-1 Control Register (EE1CR). . . . . . . . . . . . . . . . . . .99
6-3 EEPROM-1 Array Configuration Register (EE1ACR). . . . . . .101
6-4 EEPROM-1 Nonvolatile Register (EE1NVR) . . . . . . . . . . . . .103
6-5 EE1DIV Divider High Register (EE1DIVH) . . . . . . . . . . . . . . .104
6-6 EE1DIV Divider Low Register (EE1DIVL). . . . . . . . . . . . . . . .104
6-7 EEPROM-1 Divider Non-Volatile Register High (EE1DIVHNVR))
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .106
6-8 EEPROM-1 Divider Non-Volatile Register Low (EE1DIVLNVR)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .106
List of Figures
Technical Data MC68HC908AZ60A — Rev 2.0
20 List of Figures MOTOROLA
7-1 EEPROM-2 Register Summary . . . . . . . . . . . . . . . . . . . . . . .111
7-2 EEPROM-2 Control Register (EE2CR). . . . . . . . . . . . . . . . . .119
7-3 EEPROM-2 Array Configuration Register (EE2ACR). . . . . . .121
7-4 EEPROM-2 Nonvolatile Register (EE2NVR) . . . . . . . . . . . . .123
7-5 EE2DIV Divider High Register (EE2DIVH) . . . . . . . . . . . . . . .124
7-6 EE2DIV Divider Low Register (EE2DIVL). . . . . . . . . . . . . . . .124
7-7 EEPROM-2 Divider Non-Volatile Register High (EE2DIVHNVR))
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .126
7-8 EEPROM-2 Divider Non-Volatile Register Low (EE2DIVLNVR)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .126
8-1 CPU registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .130
8-2 Accumulator (A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .131
8-3 Index register (H:X). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .131
8-4 Stack pointer (SP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .132
8-5 Program counter (PC). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .133
8-6 Condition code register (CCR) . . . . . . . . . . . . . . . . . . . . . . . .133
9-1 SIM Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .149
9-2 SIM I/O Register Summary. . . . . . . . . . . . . . . . . . . . . . . . . . .149
9-3 CGM Clock Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .151
9-4 External Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .153
9-5 Internal Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .153
9-6 Sources of Internal Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . .154
9-7 POR Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .155
9-8 Interrupt Entry. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .158
9-9 Interrupt Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .159
9-10 Interrupt Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .160
9-11 Interrupt Recognition Example . . . . . . . . . . . . . . . . . . . . . . . .161
9-12 Wait Mode Entry Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . .163
9-13 Wait Recovery from Interrupt or Break . . . . . . . . . . . . . . . . . .163
9-14 Wait Recovery from Internal Reset. . . . . . . . . . . . . . . . . . . . .164
9-15 Stop Mode Entry Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . .165
9-16 Stop Mode Recovery from Interrupt or Break . . . . . . . . . . . . .165
9-17 SIM Break Status Register (SBSR) . . . . . . . . . . . . . . . . . . . .166
9-18 SIM Reset Status Register (SRSR) . . . . . . . . . . . . . . . . . . . .167
9-19 SIM Break Flag Control Register (SBFCR) . . . . . . . . . . . . . .168
10-1 CGM Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .172
10-2 I/O Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .173
10-3 CGM External Connections . . . . . . . . . . . . . . . . . . . . . . . . . .181
List of Figures
MC68HC908AZ60A — Rev 2.0 Technical Data
MOTOROLA List of Figures 21
10-4 PLL Control Register (PCTL) . . . . . . . . . . . . . . . . . . . . . . . . .183
10-5 PLL Bandwidth Control Register (PBWC) . . . . . . . . . . . . . . .185
10-6 PLL Programming Register (PPG) . . . . . . . . . . . . . . . . . . . . .187
11-1 Configuration Register (CONFIG-1) . . . . . . . . . . . . . . . . . . . .198
12-1 Configuration Register (CONFIG-2) . . . . . . . . . . . . . . . . . . . .201
13-1 Break Module Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . .204
13-2 I/O Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .205
13-3 Break Status and Control Register (BSCR) . . . . . . . . . . . . . .207
13-4 Break Address Registers (BRKH and BRKL) . . . . . . . . . . . . .208
14-1 Monitor Mode Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .211
14-2 Monitor Data Format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .213
14-3 Sample Monitor Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . .213
14-4 Read Transaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .214
14-5 Break Transaction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .214
14-6 Monitor Mode Entry Timing. . . . . . . . . . . . . . . . . . . . . . . . . . .220
15-1 COP Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .225
15-2 COP Control Register (COPCTL). . . . . . . . . . . . . . . . . . . . . .227
16-1 LVI Module Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . .231
16-2 LVI I/O Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . .232
16-3 LVI Status Register (LVISR). . . . . . . . . . . . . . . . . . . . . . . . . .233
17-1 IRQ Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .236
17-2 IRQ Interrupt Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . .238
17-3 IRQ Status and Control Register (ISCR) . . . . . . . . . . . . . . . .240
18-1 SCI Module Block Diagram . . . . . . . . . . . . . . . . . . . . . . . .246
18-2 SCI I/O Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . .247
18-3 SCI Data Formats. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .248
18-4 SCI Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .250
18-5 SCI Transmitter I/O Register Summary . . . . . . . . . . . . . . . . .251
18-6 SCI Receiver Block Diagram . . . . . . . . . . . . . . . . . . . . . .254
18-7 SCI I/O Receiver Register Summary . . . . . . . . . . . . . . . . . . .255
18-8 Receiver Data Sampling. . . . . . . . . . . . . . . . . . . . . . . . . . . . .257
18-9 Slow Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .259
18-10 Fast Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .260
18-11 SCI Control Register 1 (SCC1). . . . . . . . . . . . . . . . . . . . . . . .266
18-12 SCI Control Register 2 (SCC2). . . . . . . . . . . . . . . . . . . . . . . .269
18-13 SCI Control Register 3 (SCC3). . . . . . . . . . . . . . . . . . . . . . . .272
18-14 SCI Status Register 1 (SCS1) . . . . . . . . . . . . . . . . . . . . . . . .274
18-15 Flag Clearing Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . .276
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