Clock Generator Module (CGM)
Technical Data MC68HC908AZ60A — Rev 2.0
174 Clock Generator Module (CGM) MOTOROLA
• Loop filter
• Lock detector
The operating range of the VCO is programmable for a wide range of
frequencies and for maximum immunity to external noise, including
supply and CGMXFC noise. The VCO frequency is bound to a range
from roughly one-half to twice the center-of-range frequency, f
CGMVRS
.
Modulating the voltage on the CGMXFC pin changes the frequency
within this range. By design, f
CGMVRS
is equal to the nominal center-of-
range frequency, f
NOM
, (4.9152 MHz) times a linear factor L or (L)f
NOM
.
CGMRCLK is the PLL reference clock, a buffered version of CGMXCLK.
CGMRCLK runs at a frequency, f
CGMRCLK
, and is fed to the PLL through
a buffer. The buffer output is the final reference clock, CGMRDV,
running at a frequency f
CGMRDV
=f
CGMRCLK
.
The VCO’s output clock, CGMVCLK, running at a frequency f
CGMVCLK
,
is fed back through a programmable modulo divider. The modulo divider
reduces the VCO clock by a factor, N. The divider’s output is the VCO
feedback clock, CGMVDV, running at a frequency
f
CGMVDV
=f
CGMVCLK
/N. See Programming the PLL for more
information.
The phase detector then compares the VCO feedback clock, CGMVDV,
with the final reference clock, CGMRDV. A correction pulse is generated
based on the phase difference between the two signals. The loop filter
then slightly alters the dc voltage on the external capacitor connected to
CGMXFC based on the width and direction of the correction pulse. The
filter can make fast or slow corrections depending on its mode, as
described in Acquisition and Tracking Modes on page 175. The value
of the external capacitor and the reference frequency determines the
speed of the corrections and the stability of the PLL.
The lock detector compares the frequencies of the VCO feedback clock,
CGMVDV, and the final reference clock, CGMRDV. Therefore, the
speed of the lock detector is directly proportional to the final reference
frequency, f
CGMRDV
. The circuit determines the mode of the PLL and the
lock condition based on this comparison.
