MC68HC908AZ60A — Rev 2.0 Technical Data

MOTOROLA Clock Generator Module (CGM) 169

Technical Data — MC68HC908AZ60A

Section 10. Clock Generator Module (CGM)

10.1 Contents

10.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .170

10.3 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .170

10.4 Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . .171

10.4.1 Crystal Oscillator Circuit . . . . . . . . . . . . . . . . . . . . . . . . .171

10.4.2 Phase-Locked Loop Circuit (PLL). . . . . . . . . . . . . . . . . .173

10.4.2.1 Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .173

10.4.2.2 Acquisition and Tracking Modes . . . . . . . . . . . . . . . .175

10.4.2.3 Manual and Automatic PLL Bandwidth Modes . . . . .175

10.4.2.4 Programming the PLL . . . . . . . . . . . . . . . . . . . . . . . . .177

10.4.2.5 Special Programming Exceptions . . . . . . . . . . . . . . .179

10.4.3 Base Clock Selector Circuit . . . . . . . . . . . . . . . . . . . . . .179

10.4.4 CGM External Connections . . . . . . . . . . . . . . . . . . . . . . .180

10.5 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .181

10.5.1 Crystal Amplifier Input Pin (OSC1) . . . . . . . . . . . . . . . . .181

10.5.2 Crystal Amplifier Output Pin (OSC2) . . . . . . . . . . . . . . .181

10.5.3 External Filter Capacitor Pin (CGMXFC) . . . . . . . . . . . .181

10.5.4 Analog Power Pin (V

DDA

). . . . . . . . . . . . . . . . . . . . . . . . .182

10.5.5 Oscillator Enable Signal (SIMOSCEN) . . . . . . . . . . . . . .182

10.5.6 Crystal Output Frequency Signal (CGMXCLK) . . . . . . .182

10.5.7 CGM Base Clock Output (CGMOUT) . . . . . . . . . . . . . . .182

10.5.8 CGM CPU Interrupt (CGMINT) . . . . . . . . . . . . . . . . . . . . .182

10.6 CGM Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .183

10.6.1 PLL Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . .183

10.6.2 PLL Bandwidth Control Register . . . . . . . . . . . . . . . . . .185

10.6.3 PLL Programming Register. . . . . . . . . . . . . . . . . . . . . . .187

10.7 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .189

10.8 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .189

Clock Generator Module (CGM)

Technical Data MC68HC908AZ60A — Rev 2.0

170 Clock Generator Module (CGM) MOTOROLA

10.8.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .189

10.8.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .190

10.9 CGM During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . .190

10.10 Acquisition/Lock Time Specifications . . . . . . . . . . . . . . . .190

10.10.1 Acquisition/Lock Time Definitions . . . . . . . . . . . . . . . . .190

10.10.2 Parametric Influences on Reaction Time . . . . . . . . . . . .192

10.10.3 Choosing a Filter Capacitor . . . . . . . . . . . . . . . . . . . . . .193

10.10.4 Reaction Time Calculation . . . . . . . . . . . . . . . . . . . . . . .193

10.2 Introduction

The CGM generates the crystal clock signal, CGMXCLK, which operates

at the frequency of the crystal. The CGM also generates the base clock

signal, CGMOUT, from which the system clocks are derived. CGMOUT

is based on either the crystal clock divided by two or the phase-locked

loop (PLL) clock, CGMVCLK, divided by two. The PLL is a frequency

generator designed for use with 1-MHz to 8-MHz crystals or ceramic

resonators. The PLL can generate an 8-MHz bus frequency without

using high frequency crystals.

10.3 Features

Features of the CGM include:

• Phase-Locked Loop with Output Frequency in Integer Multiples of

the Crystal Reference

• Programmable Hardware Voltage-Controlled Oscillator (VCO) for

Low-Jitter Operation

• Automatic Bandwidth Control Mode for Low-Jitter Operation

• Automatic Frequency Lock Detector

• CPU Interrupt on Entry or Exit from Locked Condition

Clock Generator Module (CGM)

Functional Description

MC68HC908AZ60A — Rev 2.0 Technical Data

MOTOROLA Clock Generator Module (CGM) 171

10.4 Functional Description

The CGM consists of three major submodules:

• Crystal oscillator circuit — The crystal oscillator circuit generates

the constant crystal frequency clock, CGMXCLK.

• Phase-locked loop (PLL) — The PLL generates the

programmable VCO frequency clock CGMVCLK.

• Base clock selector circuit — This software-controlled circuit

selects either CGMXCLK divided by two or the VCO clock,

CGMVCLK, divided by two as the base clock, CGMOUT. The

system clocks are derived from CGMOUT.

Figure 10-1 shows the structure of the CGM.

10.4.1 Crystal Oscillator Circuit

The crystal oscillator circuit consists of an inverting amplifier and an

external crystal. The OSC1 pin is the input to the amplifier and the OSC2

pin is the output. The SIMOSCEN signal enables the crystal oscillator

circuit.

The CGMXCLK signal is the output of the crystal oscillator circuit and

runs at a rate equal to the crystal frequency. CGMXCLK is then buffered

to produce CGMRCLK, the PLL reference clock.

CGMXCLK can be used by other modules which require precise timing

for operation. The duty cycle of CGMXCLK is not guaranteed to be 50%

and depends on external factors, including the crystal and related

external components.

An externally generated clock also can feed the OSC1 pin of the crystal

oscillator circuit. Connect the external clock to the OSC1 pin and let the

OSC2 pin float.

Part #	8A/S6
Description	Incandescent S Light Lamp
Category	LAMP
Availability	In Stock
Qty	2

8A/S6

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