System Integration Module (SIM)

SIM Bus Clock Control and Generation

MC68HC908AZ60A — Rev 2.0 Technical Data

MOTOROLA System Integration Module (SIM) 151

9.3.2 Clock Startup from POR or LVI Reset

When the power-on reset module or the low-voltage inhibit module

generates a reset, the clocks to the CPU and peripherals are inactive

and held in an inactive phase until after 4096 CGMXCLK cycles. The

RST

pin is driven low by the SIM during this entire period. The bus clocks

start upon completion of the timeout.

Figure 9-3. CGM Clock Signals

9.3.3 Clocks in Stop Mode and Wait Mode

Upon exit from stop mode by an interrupt, break, or reset, the SIM allows

CGMXCLK to clock the SIM counter. The CPU and peripheral clocks do

not become active until after the stop delay timeout. This timeout is

selectable as 4096 or 32 CGMXCLK cycles. See Stop Mode on page

164.

In wait mode, the CPU clocks are inactive. Refer to the wait mode

subsection of each module to see if the module is active or inactive in

wait mode. Some modules can be programmed to be active in wait

mode.

PLL

OSC1

CGMXCLK

÷ 2

BUS CLOCK

GENERATORS

SIM

CGM

SIM COUNTER

PTC3

MONITOR MODE

CLOCK

SELECT

CIRCUIT

CGMVCLK

BCS

÷ 2

CGMOUT

*When S = 1,

CGMOUT = B

USER MODE

System Integration Module (SIM)

Technical Data MC68HC908AZ60A — Rev 2.0

152 System Integration Module (SIM) MOTOROLA

9.4 Reset and System Initialization

The MCU has these reset sources:

• Power-on reset module (POR)

• External reset pin (RST)

• Computer operating properly module (COP)

• Low-voltage inhibit module (LVI)

• Illegal opcode

• Illegal address

All of these resets produce the vector $FFFE–FFFF ($FEFE–FEFF in

monitor mode) and assert the internal reset signal (IRST). IRST causes

all registers to be returned to their default values and all modules to be

returned to their reset states.

An internal reset clears the SIM counter (see SIM Counter on page

156), but an external reset does not. Each of the resets sets a

corresponding bit in the SIM reset status register (SRSR) (see SIM

Registers on page 165).

9.4.1 External Pin Reset

Pulling the asynchronous RST pin low halts all processing. The PIN bit

of the SIM reset status register (SRSR) is set as long as RST

is held low

for a minimum of 67 CGMXCLK cycles, assuming that neither the POR

nor the LVI was the source of the reset. See Table 9-3 for details. Figure

9-4 shows the relative timing.

Table 9-3. PIN Bit Set Timing

Reset Type Number of Cycles Required to Set PIN

POR/LVI 4163 (4096 + 64 + 3)

All others 67 (64 + 3)

System Integration Module (SIM)

Reset and System Initialization

MC68HC908AZ60A — Rev 2.0 Technical Data

MOTOROLA System Integration Module (SIM) 153

Figure 9-4. External Reset Timing

9.4.2 Active Resets from Internal Sources

All internal reset sources actively pull the RST

pin low for 32 CGMXCLK

cycles to allow resetting of external peripherals. The internal reset signal

IRST continues to be asserted for an additional 32 cycles (see Figure 9-

5). An internal reset can be caused by an illegal address, illegal opcode,

COP timeout, LVI, or POR (see Figure 9-6). Note that for LVI or POR

resets, the SIM cycles through 4096 CGMXCLK cycles during which the

SIM forces the RST pin low. The internal reset signal then follows the

sequence from the falling edge of RST

shown in Figure 9-5.

The COP reset is asynchronous to the bus clock.

The active reset feature allows the part to issue a reset to peripherals

and other chips within a system built around the MCU.

Figure 9-5. Internal Reset Timing

RST

IAB

VECT H VECT L

CGMOUT

IRST

RST

RST PULLED LOW BY MCU

IAB

32 CYCLES 32 CYCLES

VECTOR HIGH

CGMXCLK

Part #	8A/S6
Description	Incandescent S Light Lamp
Category	LAMP
Availability	In Stock
Qty	2

8A/S6

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Technical Document