System Integration Module (SIM)
Technical Data MC68HC908AZ60A — Rev 2.0
150 System Integration Module (SIM) MOTOROLA
Table 9-2 shows the internal signal names used in this section.
9.3 SIM Bus Clock Control and Generation
The bus clock generator provides system clock signals for the CPU and
peripherals on the MCU. The system clocks are generated from an
incoming clock, CGMOUT, as shown in Figure 9-3. This clock can come
from either an external oscillator or from the on-chip PLL. (See Clock
Generator Module (CGM) on page 169).
9.3.1 Bus Timing
In user mode, the internal bus frequency is either the crystal oscillator
output (CGMXCLK) divided by four or the PLL output (CGMVCLK)
divided by four. (See Clock Generator Module (CGM) on page 169).
Table 9-1. I/O Register Address Summary
Register SBSR SRSR SBFCR
Address $FE00 $FE01 $FE03
Table 9-2. Signal Name Conventions
Signal Name Description
CGMXCLK
Buffered Version of OSC1 from Clock Generator Module
(CGM)
CGMVCLK PLL Output
CGMOUT
PLL-Based or OSC1-Based Clock Output from CGM Module
(Bus Clock = CGMOUT Divided by Two)
IAB Internal Address Bus
IDB Internal Data Bus
PORRST Signal from the Power-On Reset Module to the SIM
IRST Internal Reset Signal
R/W
Read/Write Signal
