Central Processor Unit (CPU)

Technical Data MC68HC908AZ60A — Rev 2.0

142 Central Processor Unit (CPU) MOTOROLA

LDA #opr

LDA opr

LDA opr,X

LDA ,X

LDA opr,SP

Load A from M A

← (M) 0 – – ↕↕–

IMM

DIR

EXT

IX2

IX1

IX

SP1

SP2

A6

B6

C6

D6

E6

F6

9E

E6

9E

D6

ii

dd

hh

ll

ee

ff

ee

ff

2

3

4

3

2

4

5

LDHX #opr

LDHX opr

Load H:X from M H:X

← (M:M + 1) 0––↕↕–

IMM

DIR

45

55

ii jj

dd

3

4

LDX #opr

LDX opr

LDX opr,X

LDX ,X

LDX opr,SP

Load X from M X

← (M) 0 – – ↕↕–

IMM

DIR

EXT

IX2

IX1

IX

SP1

SP2

AE

BE

CE

DE

EE

FE

9E

EE

9E

DE

ii

dd

hh

ll

ee

ff

ee

ff

2

3

4

3

2

4

5

LSL opr

LSLA

LSLX

LSL opr,X

LSL ,X

LSL opr,SP

Logical Shift Left

(Same as ASL)

↕ ––↕↕↕

DIR

INH

IX1

IX

SP1

38

48

58

68

78

9E

68

dd

ff

4

1

4

3

5

LSR opr

LSRA

LSRX

LSR opr,X

LSR ,X

LSR opr,SP

Logical Shift Right ↕ ––0↕↕

DIR

INH

IX1

IX

SP1

34

44

54

64

74

9E

64

dd

ff

4

1

4

3

5

MOV opr,opr

MOV opr,X+

MOV #opr,opr

MOV X+,opr

Move

(M)

Destination

← (M)

Source

H:X ← (H:X) + 1 (IX+D, DIX+)

0––↕↕–

DD

DIX+

IMD

IX+D

4E

5E

6E

7E

dd

ii

dd

5

4

MUL Unsigned multiply X:A

← (X) × (A) –0–––0INH 42 5

NEG opr

NEGA

NEGX

NEG opr,X

NEG ,X

NEG opr,SP

Negate (Two’s Complement)

M

← –(M) = $00 – (M)

A

← –(A) = $00 – (A)

X

← –(X) = $00 – (X)

M

← –(M) = $00 – (M)

M

← –(M) = $00 – (M)

↕ ––↕↕↕

DIR

INH

IX1

IX

SP1

30

40

50

60

70

9E

60

dd

ff

4

1

4

3

5

NOP No Operation None – – – – – – INH 9D 1

NSA Nibble Swap A A

← (A[3:0]:A[7:4]) – – – – – – INH 62 3

Table 8-1. Instruction Set Summary (Continued)

Source

Form

Operation Description

Effect on

CCR

Address

Mode

Opcode

Operand

Cycles

VHI NZC

C

b0

b7

0

b0

b7

C0

Central Processor Unit (CPU)

Instruction Set Summary

MC68HC908AZ60A — Rev 2.0 Technical Data

MOTOROLA Central Processor Unit (CPU) 143

ORA #opr

ORA opr

ORA opr,X

ORA ,X

ORA opr,SP

Inclusive OR A and M A

← (A) | (M) 0 – – ↕↕–

IMM

DIR

EXT

IX2

IX1

IX

SP1

SP2

AA

BA

CA

DA

EA

FA

9E

EA

9E

DA

ii

dd

hh

ll

ee

ff

ee

ff

2

3

4

3

2

4

5

PSHA Push A onto Stack Push (A); SP

← (SP) – 1 ––––––INH 87 2

PSHH Push H onto Stack Push (H); SP

← (SP) – 1 ––––––INH 8B 2

PSHX Push X onto Stack Push (X); SP

← (SP) – 1 ––––––INH 89 2

PULA Pull A from Stack SP

← (SP + 1); Pull (A) ––––––INH 86 2

PULH Pull H from Stack SP

← (SP + 1); Pull (H) ––––––INH 8A 2

PULX Pull X from Stack SP

← (SP + 1); Pull (X) ––––––INH 88 2

ROL opr

ROLA

ROLX

ROL opr,X

ROL ,X

ROL opr,SP

Rotate Left through Carry ↕ ––↕↕↕

DIR

INH

IX1

IX

SP1

39

49

59

69

79

9E

69

dd

ff

4

1

4

3

5

ROR opr

RORA

RORX

ROR opr,X

ROR ,X

ROR opr,SP

Rotate Right through Carry ↕ ––↕↕↕

DIR

INH

IX1

IX

SP1

36

46

56

66

76

9E

66

dd

ff

4

1

4

3

5

RSP Reset Stack Pointer SP

← $FF ––––––INH 9C 1

RTI Return from Interrupt

SP

← (SP) + 1; Pull (CCR)

SP

← (SP) + 1; Pull (A)

SP

← (SP) + 1; Pull (X)

SP

← (SP) + 1; Pull (PCH)

SP

← (SP) + 1; Pull (PCL)

↕↕↕↕↕↕INH 80 7

RTS Return from Subroutine

SP

← SP + 1; Pull (PCH)

SP

← SP + 1; Pull (PCL)

––––––INH 81 4

SBC #opr

SBC opr

SBC opr,X

SBC ,X

SBC opr,SP

Subtract with Carry A

← (A) – (M) – (C) ↕ ––↕↕↕

IMM

DIR

EXT

IX2

IX1

IX

SP1

SP2

A2

B2

C2

D2

E2

F2

9E

E2

9E

D2

ii

dd

hh

ll

ee

ff

ee

ff

2

3

4

3

2

4

5

SEC Set Carry Bit C

← 1 –––––1INH 99 1

Table 8-1. Instruction Set Summary (Continued)

Source

Form

Operation Description

Effect on

CCR

Address

Mode

Opcode

Operand

Cycles

VHI NZC

C

b0

b7

b0

b7

C

Central Processor Unit (CPU)

Technical Data MC68HC908AZ60A — Rev 2.0

144 Central Processor Unit (CPU) MOTOROLA

SEI Set Interrupt Mask I ← 1 ––1–––INH 9B 2

STA opr

STA opr,X

STA ,X

STA opr,SP

Store A in M M

← (A) 0 – – ↕↕–

DIR

EXT

IX2

IX1

IX

SP1

SP2

B7

C7

D7

E7

F7

9E

E7

9E

D7

dd

hh

ll

ee

ff

ee

ff

3

4

3

2

4

5

STHX opr Store H:X in M (M:M + 1)

← (H:X) 0 – – ↕↕– DIR 35 dd 4

STOP Enable IRQ

Pin; Stop Oscillator I ← 0; Stop Oscillator – – 0 – – – INH 8E 1

STX opr

STX opr,X

STX ,X

STX opr,SP

Store X in M M

← (X) 0 – – ↕↕–

DIR

EXT

IX2

IX1

IX

SP1

SP2

BF

CF

DF

EF

FF

9E

EF

9E

DF

dd

hh

ll

ee

ff

ee

ff

3

4

3

2

4

5

SUB #opr

SUB opr

SUB opr,X

SUB ,X

SUB opr,SP

Subtract A

← (A) – (M) ↕ ––↕↕↕

IMM

DIR

EXT

IX2

IX1

IX

SP1

SP2

A0

B0

C0

D0

E0

F0

9E

E0

9E

D0

ii

dd

hh

ll

ee

ff

ee

ff

2

3

4

3

2

4

5

SWI Software Interrupt

PC

← (PC) + 1; Push (PCL)

SP

← (SP) – 1; Push (PCH)

SP

← (SP) – 1; Push (X)

SP

← (SP) – 1; Push (A)

SP

← (SP) – 1; Push (CCR)

SP

← (SP) – 1; I ← 1

PCH

← Interrupt Vector High Byte

PCL

← Interrupt Vector Low Byte

––1–––INH 83 9

TAP Transfer A to CCR CCR

← (A) ↕↕↕↕↕↕INH 84 2

TAX Transfer A to X X

← (A) ––––––INH 97 1

TPA Transfer CCR to A A

← (CCR) – – – – – – INH 85 1

TST opr

TSTA

TSTX

TST opr,X

TST ,X

TST opr,SP

Test for Negative or Zero (A) – $00 or (X) – $00 or (M) – $00 0 – – ↕↕–

DIR

INH

IX1

IX

SP1

3D

4D

5D

6D

7D

9E

6D

dd

ff

3

1

3

2

4

TSX Transfer SP to H:X H:X

← (SP) + 1 ––––––INH 95 2

Table 8-1. Instruction Set Summary (Continued)

Source

Form

Operation Description

Effect on

CCR

Address

Mode

Opcode

Operand

Cycles

VHI NZC

Part #	8A/S6
Description	Incandescent S Light Lamp
Category	LAMP
Availability	In Stock
Qty	2

8A/S6

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Technical Document