Central Processor Unit (CPU)
Instruction Set Summary
MC68HC908AZ60A — Rev 2.0 Technical Data
MOTOROLA Central Processor Unit (CPU) 139
BMC rel Branch if Interrupt Mask Clear PC ← (PC) + 2 + rel ? (I) = 0 ––––––REL 2C rr 3
BMI rel Branch if Minus PC
← (PC) + 2 + rel ? (N) = 1 ––––––REL 2B rr 3
BMS rel Branch if Interrupt Mask Set PC
← (PC) + 2 + rel ? (I) = 1 ––––––REL 2D rr 3
BNE rel Branch if Not Equal PC
← (PC) + 2 + rel ? (Z) = 0 ––––––REL 26 rr 3
BPL rel Branch if Plus PC
← (PC) + 2 + rel ? (N) = 0 ––––––REL 2A rr 3
BRA rel Branch Always PC
← (PC) + 2 + rel ––––––REL 20 rr 3
BRCLR
n,opr,rel
Branch if Bit n in M Clear PC
← (PC) + 3 + rel ? (Mn) = 0 – – – – – ↕
DIR
(b0)
DIR
(b1)
DIR
(b2)
DIR
(b3)
DIR
(b4)
DIR
(b5)
DIR
(b6)
DIR
(b7)
01
03
05
07
09
0B
0D
0F
dd
rr
dd
rr
dd
rr
dd
rr
dd
rr
dd
rr
dd
rr
dd
rr
5
5
5
5
5
5
5
5
BRN rel Branch Never PC
← (PC) + 2 ––––––REL 21 rr 3
BRSET
n,opr,rel
Branch if Bit n in M Set PC
← (PC) + 3 + rel ? (Mn) = 1 – – – – – ↕
DIR
(b0)
DIR
(b1)
DIR
(b2)
DIR
(b3)
DIR
(b4)
DIR
(b5)
DIR
(b6)
DIR
(b7)
00
02
04
06
08
0A
0C
0E
dd
rr
dd
rr
dd
rr
dd
rr
dd
rr
dd
rr
dd
rr
dd
rr
5
5
5
5
5
5
5
5
BSET n,opr Set Bit n in M Mn
← 1 ––––––
DIR
(b0)
DIR
(b1)
DIR
(b2)
DIR
(b3)
DIR
(b4)
DIR
(b5)
DIR
(b6)
DIR
(b7)
10
12
14
16
18
1A
1C
1E
dd
dd
dd
dd
dd
dd
dd
dd
4
4
4
4
4
4
4
4
Table 8-1. Instruction Set Summary (Continued)
Source
Form
Operation Description
Effect on
CCR
Address
Mode
Opcode
Operand
Cycles
VHI NZC
