Central Processor Unit (CPU)

Technical Data MC68HC908AZ60A — Rev 2.0

136 Central Processor Unit (CPU) MOTOROLA

8.6 Low-power modes

The WAIT and STOP instructions put the MCU in low--power

consumption standby modes.

8.6.1 WAIT mode

The WAIT instruction:

• clears the interrupt mask (I bit) in the condition code register,

enabling interrupts. After exit from WAIT mode by interrupt, the I

bit remains clear. After exit by reset, the I bit is set.

• Disables the CPU clock

8.6.2 STOP mode

The STOP instruction:

• clears the interrupt mask (I bit) in the condition code register,

enabling external interrupts. After exit from STOP mode by

external interrupt, the I bit remains clear. After exit by reset, the I

bit is set.

• Disables the CPU clock

After exiting STOP mode, the CPU clock begins running after the

oscillator stabilization delay.

8.7 CPU during break interrupts

If the break module is enabled, a break interrupt causes the CPU to

execute the software interrupt instruction (SWI) at the completion of the

current CPU instruction. See Break Module (BRK). The program

counter vectors to $FFFC–$FFFD ($FEFC–$FEFD in monitor mode).

A return-from-interrupt instruction (RTI) in the break routine ends the

break interrupt and returns the MCU to normal operation if the break

interrupt has been deasserted.

Central Processor Unit (CPU)

Instruction Set Summary

MC68HC908AZ60A — Rev 2.0 Technical Data

MOTOROLA Central Processor Unit (CPU) 137

8.8 Instruction Set Summary

Table 8-1 provides a summary of the M68HC08 instruction set.

Table 8-1. Instruction Set Summary

Source

Form

Operation Description

Effect on

CCR

Address

Mode

Opcode

Operand

Cycles

VHI NZC

ADC #opr

ADC opr

ADC opr,X

ADC ,X

ADC opr,SP

Add with Carry A

← (A) + (M) + (C) ↕↕– ↕↕↕

IMM

DIR

EXT

IX2

IX1

IX

SP1

SP2

A9

B9

C9

D9

E9

F9

9E

E9

9E

D9

ii

dd

hh

ll

ee

ff

ee

ff

2

3

4

3

2

4

5

ADD #opr

ADD opr

ADD opr,X

ADD ,X

ADD opr,SP

Add without Carry A

← (A) + (M) ↕↕– ↕↕↕

IMM

DIR

EXT

IX2

IX1

IX

SP1

SP2

AB

BB

CB

DB

EB

FB

9E

EB

9E

DB

ii

dd

hh

ll

ee

ff

ee

ff

2

3

4

3

2

4

5

AIS #opr

Add Immediate Value (Signed) to

SP

← (SP) + (16 « M)

––––––IMM A7 ii 2

AIX #opr

Add Immediate Value (Signed) to

H:X

← (H:X) + (16 « M)

––––––IMM AF ii 2

AND #opr

AND opr

AND opr,X

AND ,X

AND opr,SP

Logical AND A

← (A) & (M) 0 – – ↕↕–

IMM

DIR

EXT

IX2

IX1

IX

SP1

SP2

A4

B4

C4

D4

E4

F4

9E

E4

9E

D4

ii

dd

hh

ll

ee

ff

ee

ff

2

3

4

3

2

4

5

ASL opr

ASLA

ASLX

ASL opr,X

ASL ,X

ASL opr,SP

Arithmetic Shift Left

(Same as LSL)

↕ ––↕↕↕

DIR

INH

IX1

IX

SP1

38

48

58

68

78

9E

68

dd

ff

4

1

4

3

5

ASR opr

ASRA

ASRX

ASR opr,X

ASR opr,SP

Arithmetic Shift Right ↕ ––↕↕↕

DIR

INH

IX1

IX

SP1

37

47

57

67

77

9E

67

dd

ff

4

1

4

3

5

C

b0

b7

0

b0

b7

C

Central Processor Unit (CPU)

Technical Data MC68HC908AZ60A — Rev 2.0

138 Central Processor Unit (CPU) MOTOROLA

BCC rel Branch if Carry Bit Clear PC ← (PC) + 2 + rel ? (C) = 0 – – – – – – REL 24 rr 3

BCLR n, opr Clear Bit n in M Mn

← 0 ––––––

DIR

(b0)

DIR

(b1)

DIR

(b2)

DIR

(b3)

DIR

(b4)

DIR

(b5)

DIR

(b6)

DIR

(b7)

11

13

15

17

19

1B

1D

1F

dd

4

BCS rel

Branch if Carry Bit Set (Same as

BLO)

PC

← (PC) + 2 + rel ? (C) = 1 ––––––REL 25 rr 3

BEQ rel Branch if Equal PC

← (PC) + 2 + rel ? (Z) = 1 ––––––REL 27 rr 3

BGE opr

Branch if Greater Than or Equal

To (Signed Operands)

PC

← (PC) + 2 + rel ? (N ⊕ V) = 0

––––––REL 90 rr 3

BGT opr

Branch if Greater Than (Signed

Operands)

PC

← (PC) + 2 + rel ? (Z) | (N ⊕ V) =

0

––––––REL 92 rr 3

BHCC rel Branch if Half Carry Bit Clear PC

← (PC) + 2 + rel ? (H) = 0 ––––––REL 28 rr 3

BHCS rel Branch if Half Carry Bit Set PC

← (PC) + 2 + rel ? (H) = 1 ––––––REL 29 rr 3

BHI rel Branch if Higher PC

← (PC) + 2 + rel ? (C) | (Z) = 0 – – – – – – REL 22 rr 3

BHS rel

Branch if Higher or Same

(Same as BCC)

PC

← (PC) + 2 + rel ? (C) = 0 ––––––REL 24 rr 3

BIH rel Branch if IRQ

Pin High PC ← (PC) + 2 + rel ? IRQ = 1 ––––––REL 2F rr 3

BIL rel Branch if IRQ

Pin Low PC ← (PC) + 2 + rel ? IRQ = 0 ––––––REL 2E rr 3

BIT #opr

BIT opr

BIT opr,X

BIT ,X

BIT opr,SP

Bit Test (A) & (M) 0 – – ↕↕–

IMM

DIR

EXT

IX2

IX1

IX

SP1

SP2

A5

B5

C5

D5

E5

F5

9E

E5

9E

D5

ii

dd

hh

ll

ee

ff

ee

ff

2

3

4

3

2

4

5

BLE opr

Branch if Less Than or Equal To

(Signed Operands)

PC

← (PC) + 2 + rel ? (Z) | (N ⊕ V) =

1

––––––REL 93 rr 3

BLO rel Branch if Lower (Same as BCS) PC

← (PC) + 2 + rel ? (C) = 1 ––––––REL 25 rr 3

BLS rel Branch if Lower or Same PC

← (PC) + 2 + rel ? (C) | (Z) = 1 – – – – – – REL 23 rr 3

BLT opr

Branch if Less Than (Signed

Operands)

PC

← (PC) + 2 + rel ? (N ⊕ V) =1

––––––REL 91 rr 3

Table 8-1. Instruction Set Summary (Continued)

Source

Form

Operation Description

Effect on

CCR

Address

Mode

Opcode

Operand

Cycles

VHI NZC

Part #	8A/S6
Description	Incandescent S Light Lamp
Category	LAMP
Availability	In Stock
Qty	2

8A/S6

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