EEPROM-2 Memory
Technical Data MC68HC908AZ60A — Rev 2.0
118 EEPROM-2 Memory MOTOROLA
8. Clear EELAT bits.
(E)
NOTE: A. Setting the EELAT bit configures the address and data buses to latch
data for erasing the array. Only valid EEPROM-2 addresses will be
latched. If EELAT is set, other writes to the EE2CR will be allowed after
a valid EEPROM-2 write.
B. If more than one valid EEPROM write occurs, the last address and
data will be latched overriding the previous address and data. Once data
is written to the desired address, do not read EEPROM-2 locations other
than the written location. (Reading an EEPROM location returns the
latched data and causes the read address to be latched).
C. The EEPGM bit cannot be set if the EELAT bit is cleared or a non-
valid EEPROM address is latched. This is to ensure proper
programming sequence. Once EEPGM is set, do not read any
EEPROM-2 locations; otherwise, the current program cycle will be
unsuccessful. When EEPGM is set, the on-board programming
sequence will be activated.
D. The delay time for the EEPGM bit to be cleared in AUTO mode is less
than t
EEBYTE
/t
EEBLOCK
/t
EEBULK
. However, on other MCUs, this delay
time may be different. For forward compatibility, software should not
make any dependency on this delay time.
E. Any attempt to clear both EEPGM and EELAT bits with a single
instruction will only clear EEPGM. This is to allow time for removal of
high voltage from the EEPROM-2 array.
