EEPROM-1 Memory
Functional Description
MC68HC908AZ60A — Rev 2.0 Technical Data
MOTOROLA EEPROM-1 Memory 93
6.5.2 EEPROM-1 Timebase Requirements
A 35µs timebase is required by the EEPROM-1 control circuit for
program and erase of EEPROM content. This timebase is derived from
dividing the CGMXCLK or bus clock (selected by EEDIVCLK bit in
CONFIG-2 Register) using a timebase divider circuit controlled by the
16-bit EEPROM-1 Timebase Divider EE1DIV Register (EE1DIVH and
EE1DIVL).
As the CGMXCLK or bus clock is user selected, the EEPROM-1
Timebase Divider Register must be configured with the appropriate
value to obtain the 35 µs. The timebase divider value is calculated by
using the following formula:
EE1DIV= INT[Reference Frequency(Hz) x 35 x10
-6
+0.5]
This value is written to the EEPROM-1 Timebase Divider Register
(EE1DIVH and EE1DIVL) or programmed into the EEPROM-1
Timebase Divider Non-Volatile Register prior to any EEPROM program
or erase operations(see EEPROM-1 Configuration on page 92 and
EEPROM-1 Timebase Requirements on page 93).
6.5.3 EEPROM-1 Program/Erase Protection
The EEPROM has a special feature that designates the 16 bytes of
addresses from $08F0 to $08FF to be permanently secured. This
program/erase protect option is enabled by programming the EEPRTCT
bit in the EEPROM-1 Non-Volatile Register (EE1NVR) to a logic zero.
Once the EEPRTCT bit is programmed to 0 for the first time:
• Programming and erasing of secured locations $08F0 to $08FF is
permanently disabled.
• Secured locations $08F0 to $08FF can be read as normal.
• Programming and erasing of EE1NVR is permanently disabled.
• Bulk and Block Erase operations are disabled for the unprotected
locations $0800-$08EF, $0900-$09FF.
