FLASH-2 Memory
Technical Data MC68HC908AZ60A — Rev 2.0
80 FLASH-2 Memory MOTOROLA
ERASE — Erase Control Bit
This read/write bit configures the memory for erase operation.
ERASE is interlocked with the PGM bit such that both bits cannot be
set at the same time.
1 = Erase operation selected
0 = Erase operation unselected
PGM — Program Control Bit
This read/write bit configures the memory for program operation.
PGM is interlocked with the ERASE bit such that both bits cannot be
equal to 1 or set to 1 at the same time.
1 = Program operation selected
0 = Program operation unselected
5.4.2 FLASH-2 Block Protect Register
The FLASH-2 Block Protect Register (FL2BPR) is implemented as a
byte within the FLASH-1 memory and therefore can only be written
during a FLASH programming sequence. The value in this register
determines the starting location of the protected range within the
FLASH-2 memory.
NOTE: The FLASH-2 Block Protect Register (FL2BPR) controls the block
protection for the FLASH-2 array. However, FL2BPR is implemented
within the FLASH-1 memory array and therefore, the FLASH-1 Control
Register (FL1CR) must be used to program/erase FL2BPR.
FL2BPR[7:0] — Block Protect Register Bit7 to Bit0
These eight bits represent bits [14:7] of a 16-bit memory address. Bit-
15 is logic 1 and bits [6:0] are logic 0s.
Address: $FF81
Bit 7654321Bit 0
Read:
BPR7 BPR6 BPR5 BPR4 BPR3 BPR2 BPR1 BPR0
Write:
Figure 5-2. FLASH-2 Block Protect Register (FL2BPR)
