FLASH-1 Memory
Technical Data MC68HC908AZ60A — Rev 2.0
66 FLASH-1 Memory MOTOROLA
4.3 Functional Description
The FLASH-1 memory is an array of 32,256 bytes with two bytes of block
protection (one byte for protecting areas within FLASH-1 array and one
byte for protecting areas within FLASH-2 array) and an additional 40
bytes of user vectors on the MC68HC908AS60A and 52 bytes of user
vectors on the MC68HC908AZ60A. An erased bit reads as a logic 1 and
a programmed bit reads as a logic 0.
Memory in the FLASH-1 array is organized into rows within pages. There
are two rows of memory per page with 64 bytes per row. The minimum
erase block size is a single page,128 bytes. Programming is performed
on a per-row basis, 64 bytes at a time. Program and erase operations
are facilitated through control bits in the FLASH-1 Control Register
(FL1CR). Details for these operations appear later in this section.
The FLASH-1 memory map consists of:
• $8000–$FDFF: User Memory (32,256 bytes)
• $FF80: FLASH-1 Block Protect Register (FL1BPR)
• $FF81: FLASH-2 Block Protect Register (FL2BPR)
• $FF88: FLASH-1 Control Register (FL1CR)
• $FFCC–$FFFF: these locations are reserved for user-defined
interrupt and reset vectors (Please see Vector Addresses and
Priority on page 61 for details)
Programming tools are available from Motorola. Contact your local
Motorola representative for more information.
NOTE: A security feature prevents viewing of the FLASH contents.
(1)
1. No security feature is absolutely secure. However, Motorola’s strategy is to make reading or
copying the FLASH difficult for unauthorized users.
