Memory Map
I/O Section
MC68HC908AZ60A — Rev 2.0 Technical Data
MOTOROLA Memory Map 57
$0033
Timer A Channel 4 Register High
(TACH4H)
Read:
Bit 15 14 13 12 11 10 9 Bit 8
Write:
$0034
Timer A Channel 4 Register Low
(TACH4L)
Read:
Bit 7654321Bit 0
Write:
$0035
Timer A Channel 5 Status and
Control Register (TASC5)
Read: CH5F
CH5IE
0
MS5A ELS5B ELS5A TOV5 CH5MAX
Write: 0 R
$0036
Timer A Channel 5 Register
High (TACH5H)
Read:
Bit 15 14 13 12 11 10 9 Bit 8
Write:
$0037
Timer A Channel 5 Register
Low (TACH5L)
Read:
Bit 7654321Bit 0
Write:
$0038
Analog-to-Digital Status and
Control Register (ADSCR)
Read: COCO
AIEN ADCO ADCH4 ADCH3 ADCH2 ADCH1 ADCH0
Write: R
$0039
Analog-to-Digital Data Register
(ADR)
Read: AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0
Write:RRRRRRRR
$003A
Analog-to-Digital Input Clock
Register (ADICLK)
Read:
ADIV2 ADIV1 ADIV0 ADICLK
0000
Write: RRRR
$003B
BDLC Analog and Roundtrip Delay
Register (BARD)
Read:
ATE RXPOL
00
BO3 BO2 BO1 BO0
Write: R R
$003C BDLC Control Register 1 (BCR1)
Read:
IMSG CLKS R1 R0
00
IE WCM
Write: R R
$003D BDLC Control Register 2 (BCR2)
Read:
ALOOP DLOOP RX4XE NBFS TEOD TSIFR TMIFR1 TMIFR0
Write:
$003E
BDLC State Vector Register
(BSVR)
Read: 0 0 I3 I2 I1 I0 0 0
Write:RRRRRRRR
$003F BDLC Data Register (BDR)
Read:
BD7 BD6 BD5 BD4 BD3 BD2 BD1 BD0
Write:
$0040
Timer B Status and Control
Register (TBSCR)
Read: TOF
TOIE TSTOP
00
PS2 PS1 PS0
Write: 0 TRST R
$0041
Timer B Counter Register High
(TBCNTH)
Read: Bit 15 14 13 12 11 10 9 Bit 8
Write:RRRRRRRR
$0042
Timer B Counter Register Low
(TBCNTL)
Read: Bit 7 654321Bit 0
Write:RRRRRRRR
$0043
Timer B Modulo Register High
(TBMODH)
Read:
Bit 15 14 13 12 11 10 9 Bit 8
Write:
$0044
Timer B Modulo Register Low
(TBMODL)
Read:
Bit 7654321Bit 0
Write:
Addr.Register Name Bit 7654321Bit 0
Figure 2-2. I/O Data, Status and Control Registers (Sheet 4 of 5)
