General Description
Technical Data MC68HC908AZ60A — Rev 2.0
36 General Description MOTOROLA
BREAK MODULE
CLOCK GENERATOR
MODULE
SYSTEM INTEGRATION
MODULE
ANALOG-TO-DIGITAL
MODULE
SERIAL COMMUNICATIONS
INTERFACE MODULE
SERIAL PERIPHERAL
INTERFACE MODULE
TIMER A 6 CHANNEL
INTERFACE MODULE
LOW-VOLTAGE INHIBIT
MODULE
POWER-ON RESET
MODULE
COMPUTER OPERATING
PROPERLY MODULE
ARITHMETIC/LOGIC
UNIT (ALU)
CPU
REGISTERS
M68HC08 CPU
CONTROL AND STATUS REGISTERS — 62 BYTES
USER FLASH — 60 kBYTES
USER RAM — 2048BYTES
USER EEPROM — 1024 BYTES
MONITOR ROM — 256 BYTES
IRQ MODULE
DDRD
PTD
DDRE
PTE
PTG*
DDRG
OSC1
OSC2
CGMXFC
RST
IRQ
V
DD
V
DDA
V
SSA
PTE7/SPSCK
PTE6/MOSI
PTE5/MISO
PTE4/SS
PTE3/TACH1
PTE2/TACH0
PTE1/RxD
PTE0/TxD
PTF5/TBCH1–PTF4/TBCH0*
PTF3/TACH5-PTF0/TACH2
PTF
DDRF
PTG2/KBD2–PTG0/KBD0*
POWER
PTA
DDRA
DDRB
PTB
DDRC
PTC
PTA7–PTA0
PTB7/ATD7–PTB0/ATD0
PTC5*
PTC2/MCLK
PTC1–PTC0
V
REFH
PTH*
DDRH
PTH1/KBD4–PTH0/KBD3*
KEYBOARD INTERRUPT
MODULE*
V
SS
USER FLASH VECTOR SPACE — 52 BYTES
PTF6*
V
DDAREF
AV
SS
/V
REFL
Figure 1-2. MCU Block Diagram for the MC68HC908AS60A (64-Pin QFP and 52-pin PLCC)
PTD3/ATD11-PTD0/ATD8
PTD6/ATD14/TACLK
PTD5/ATD13
PTD4/ATD12/TBCLK
PTD7*
BDTxD
BDRxD
BYTE DATA LINK CONTROLLER
PROGRAMMABLE INTERRUPT TIMER
MODULE
* = Feature only available on the 64-pin QFP MC68HC908AS60A
PTC4
PTC3
