Timer Interface Module B (TIMB)

Functional Description

MC68HC908AZ60A — Rev 2.0 Technical Data

MOTOROLA Timer Interface Module B (TIMB) 325

Figure 20-3. PWM Period and Pulse Width

The value in the TIMB counter modulo registers and the selected

prescaler output determines the frequency of the PWM output. The

frequency of an 8-bit PWM signal is variable in 256 increments. Writing

$00FF (255) to the TIMB counter modulo registers produces a PWM

period of 256 times the internal bus clock period if the prescaler select

value is $000 (see TIMB Status and Control Register).

The value in the TIMB channel registers determines the pulse width of

the PWM output. The pulse width of an 8-bit PWM signal is variable in

256 increments. Writing $0080 (128) to the TIMB channel registers

produces a duty cycle of 128/256 or 50%.

20.4.4.1 Unbuffered PWM Signal Generation

Any output compare channel can generate unbuffered PWM pulses as

described in Pulse Width Modulation (PWM) on page 324. The pulses

are unbuffered because changing the pulse width requires writing the

new pulse width value over the value currently in the TIMB channel

registers.

An unsynchronized write to the TIMB channel registers to change a

pulse width value could cause incorrect operation for up to two PWM

periods. For example, writing a new value before the counter reaches

the old value but after the counter reaches the new value prevents any

compare during that PWM period. Also, using a TIMB overflow interrupt

routine to write a new, smaller pulse width value may cause the compare

PTEx/TCHx

PERIOD

PULSE

WIDTH

OVERFLOW OVERFLOW OVERFLOW

OUTPUT

COMPARE

OUTPUT

COMPARE

OUTPUT

COMPARE

Timer Interface Module B (TIMB)

Technical Data MC68HC908AZ60A — Rev 2.0

326 Timer Interface Module B (TIMB) MOTOROLA

to be missed. The TIMB may pass the new value before it is written to

the TIMB channel registers.

Use the following methods to synchronize unbuffered changes in the

PWM pulse width on channel x:

• When changing to a shorter pulse width, enable channel x output

compare interrupts and write the new value in the output compare

interrupt routine. The output compare interrupt occurs at the end

of the current pulse. The interrupt routine has until the end of the

PWM period to write the new value.

• When changing to a longer pulse width, enable TIMB overflow

interrupts and write the new value in the TIMB overflow interrupt

routine. The TIMB overflow interrupt occurs at the end of the

current PWM period. Writing a larger value in an output compare

interrupt routine (at the end of the current pulse) could cause two

output compares to occur in the same PWM period.

NOTE: In PWM signal generation, do not program the PWM channel to toggle

on output compare. Toggling on output compare prevents reliable 0%

duty cycle generation and removes the ability of the channel to self-

correct in the event of software error or noise. Toggling on output

compare also can cause incorrect PWM signal generation when

changing the PWM pulse width to a new, much larger value.

20.4.4.2 Buffered PWM Signal Generation

Channels 0 and 1 can be linked to form a buffered PWM channel whose

output appears on the PTF4/TBCH0 pin. The TIMB channel registers of

the linked pair alternately control the pulse width of the output.

Setting the MS0B bit in TIMB channel 0 status and control register

(TBSC0) links channel 0 and channel 1. The TIMB channel 0 registers

initially control the pulse width on the PTF4/TBCH0 pin. Writing to the

TIMB channel 1 registers enables the TIMB channel 1 registers to

synchronously control the pulse width at the beginning of the next PWM

period. At each subsequent overflow, the TIMB channel registers (0 or

1) that control the pulse width are the ones written to last. TBSC0

controls and monitors the buffered PWM function, and TIMB channel 1

Timer Interface Module B (TIMB)

Functional Description

MC68HC908AZ60A — Rev 2.0 Technical Data

MOTOROLA Timer Interface Module B (TIMB) 327

status and control register (TBSC1) is unused. While the MS0B bit is set,

the channel 1 pin, PTF5/TBCH1, is available as a general-purpose I/O

pin.

NOTE: In buffered PWM signal generation, do not write new pulse width values

to the currently active channel registers. User software should track the

currently active channel to prevent writing a new value to the active

channel. Writing to the active channel registers is the same as

generating unbuffered PWM signals.

20.4.4.3 PWM Initialization

To ensure correct operation when generating unbuffered or buffered

PWM signals, use the following initialization procedure:

1. In the TIMB status and control register (TBSC):

a. Stop the TIMB counter by setting the TIMB stop bit, TSTOP.

b. Reset the TIMB counter and prescaler by setting the TIMB

reset bit, TRST.

2. In the TIMB counter modulo registers (TBMODH–TBMODL) write

the value for the required PWM period.

3. In the TIMB channel x registers (TBCHxH–TBCHxL) write the

value for the required pulse width.

4. In TIMB channel x status and control register (TBSCx):

a. Write 0:1 (for unbuffered output compare or PWM signals) or

1:0 (for buffered output compare or PWM signals) to the

mode select bits, MSxB–MSxA (see Table 20-2).

b. Write 1 to the toggle-on-overflow bit, TOVx.

c. Write 1:0 (to clear output on compare) or 1:1 (to set output on

compare) to the edge/level select bits, ELSxB–ELSxA. The

output action on compare must force the output to the

complement of the pulse width level (see Table 20-2).

NOTE: In PWM signal generation, do not program the PWM channel to toggle

on output compare. Toggling on output compare prevents reliable 0%

duty cycle generation and removes the ability of the channel to self-

correct in the event of software error or noise. Toggling on output

Part #	8A/S6
Description	Incandescent S Light Lamp
Category	LAMP
Availability	In Stock
Qty	2

8A/S6

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