Timer Interface Module B (TIMB)

Technical Data MC68HC908AZ60A — Rev 2.0

322 Timer Interface Module B (TIMB) MOTOROLA

The free-running counter contents are transferred to the TIMB channel

340) on each proper signal transition regardless of whether the TIMB

channel flag (CH0F–CH1F in TBSC0–TBSC1 registers) is set or clear.

When the status flag is set, a CPU interrupt is generated if enabled. The

value of the count latched or “captured” is the time of the event. Because

this value is stored in the input capture register 2 bus cycles after the

actual event occurs, user software can respond to this event at a later

time and determine the actual time of the event. However, this must be

done prior to another input capture on the same pin; otherwise, the

previous time value will be lost.

By recording the times for successive edges on an incoming signal,

software can determine the period and/or pulse width of the signal. To

measure a period, two successive edges of the same polarity are

captured. To measure a pulse width, two alternate polarity edges are

captured. Software should track the overflows at the 16-bit module

counter to extend its range.

Another use for the input capture function is to establish a time

reference. In this case, an input capture function is used in conjunction

with an output compare function. For example, to activate an output

signal a specified number of clock cycles after detecting an input event

(edge), use the input capture function to record the time at which the

edge occurred. A number corresponding to the desired delay is added to

this captured value and stored to an output compare register (see TIMB

Channel Registers on page 340). Because both input captures and

output compares are referenced to the same 16-bit modulo counter, the

delay can be controlled to the resolution of the counter independent of

software latencies.

Reset does not affect the contents of the input capture channel register

(TBCHxH–TBCHxL).

Timer Interface Module B (TIMB)

Functional Description

MC68HC908AZ60A — Rev 2.0 Technical Data

MOTOROLA Timer Interface Module B (TIMB) 323

20.4.3 Output Compare

With the output compare function, the TIMB can generate a periodic

pulse with a programmable polarity, duration and frequency. When the

counter reaches the value in the registers of an output compare channel,

the TIMB can set, clear or toggle the channel pin. Output compares can

generate TIMB CPU interrupt requests.

20.4.3.1 Unbuffered Output Compare

Any output compare channel can generate unbuffered output compare

pulses as described in Output Compare on page 323. The pulses are

unbuffered because changing the output compare value requires writing

the new value over the old value currently in the TIMB channel registers.

An unsynchronized write to the TIMB channel registers to change an

output compare value could cause incorrect operation for up to two

counter overflow periods. For example, writing a new value before the

counter reaches the old value but after the counter reaches the new

value prevents any compare during that counter overflow period. Also,

using a TIMB overflow interrupt routine to write a new, smaller output

compare value may cause the compare to be missed. The TIMB may

pass the new value before it is written.

Use the following methods to synchronize unbuffered changes in the

output compare value on channel x:

• When changing to a smaller value, enable channel x output

compare interrupts and write the new value in the output compare

interrupt routine. The output compare interrupt occurs at the end

of the current output compare pulse. The interrupt routine has until

the end of the counter overflow period to write the new value.

• When changing to a larger output compare value, enable TIMB

overflow interrupts and write the new value in the TIMB overflow

interrupt routine. The TIMB overflow interrupt occurs at the end of

the current counter overflow period. Writing a larger value in an

output compare interrupt routine (at the end of the current pulse)

could cause two output compares to occur in the same counter

overflow period.

Timer Interface Module B (TIMB)

Technical Data MC68HC908AZ60A — Rev 2.0

324 Timer Interface Module B (TIMB) MOTOROLA

20.4.3.2 Buffered Output Compare

Channels 0 and 1 can be linked to form a buffered output compare

channel whose output appears on the PTF4/TBCH0 pin. The TIMB

channel registers of the linked pair alternately control the output.

Setting the MS0B bit in TIMB channel 0 status and control register

(TBSC0) links channel 0 and channel 1. The output compare value in the

TIMB channel 0 registers initially controls the output on the

PTF4/TBCH0 pin. Writing to the TIMB channel 1 registers enables the

TIMB channel 1 registers to synchronously control the output after the

TIMB overflows. At each subsequent overflow, the TIMB channel

registers (0 or 1) that control the output are the ones written to last.

TBSC0 controls and monitors the buffered output compare function and

TIMB channel 1 status and control register (TBSC1) is unused. While the

MS0B bit is set, the channel 1 pin, PTF5/TBCH1, is available as a

general-purpose I/O pin.

NOTE: In buffered output compare operation, do not write new output compare

values to the currently active channel registers. User software should

track the currently active channel to prevent writing a new value to the

active channel. Writing to the active channel registers is the same as

generating unbuffered output compares.

20.4.4 Pulse Width Modulation (PWM)

By using the toggle-on-overflow feature with an output compare channel,

the TIMB can generate a PWM signal. The value in the TIMB counter

modulo registers determines the period of the PWM signal. The channel

pin toggles when the counter reaches the value in the TIMB counter

modulo registers. The time between overflows is the period of the PWM

signal.

As Figure 20-3 shows, the output compare value in the TIMB channel

registers determines the pulse width of the PWM signal. The time

between overflow and output compare is the pulse width. Program the

TIMB to clear the channel pin on output compare if the state of the PWM

pulse is logic 1. Program the TIMB to set the pin if the state of the PWM

pulse is logic 0.

Part #	8A/S6
Description	Incandescent S Light Lamp
Category	LAMP
Availability	In Stock
Qty	2

8A/S6

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