Serial Peripheral Interface (SPI)
I/O Registers
MC68HC908AZ60A — Rev 2.0 Technical Data
MOTOROLA Serial Peripheral Interface (SPI) 311
CPOL — Clock Polarity Bit
This read/write bit determines the logic state of the SPSCK pin
between transmissions. (See Figure 19-3 and Figure 19-4.) To
transmit data between SPI modules, the SPI modules must have
identical CPOL bits. Reset clears the CPOL bit.
CPHA — Clock Phase Bit
This read/write bit controls the timing relationship between the serial
clock and SPI data. (See Figure 19-3 and Figure 19-4.) To transmit
data between SPI modules, the SPI modules must have identical
CPHA bits. When CPHA = 0, the SS
pin of the slave SPI module must
be set to logic 1 between bytes. (See Figure 19-10). Reset sets the
CPHA bit.
When CPHA = 0 for a slave, the falling edge of SS
indicates the
beginning of the transmission. This causes the SPI to leave its idle
state and begin driving the MISO pin with the MSB of its data. Once
the transmission begins, no new data is allowed into the shift register
from the data register. Therefore, the slave data register must be
loaded with the desired transmit data before the falling edge of SS
.
Any data written after the falling edge is stored in the data register and
transferred to the shift register at the current transmission.
When CPHA = 1 for a slave, the first edge of the SPSCK indicates the
beginning of the transmission. The same applies when SS is high for
a slave. The MISO pin is held in a high-impedance state, and the
incoming SPSCK is ignored. In certain cases, it may also cause the
MODF flag to be set. (See Mode Fault Error on page 299). A logic 1
on the SS pin does not in any way affect the state of the SPI state
machine.
