Serial Peripheral Interface (SPI)

Technical Data MC68HC908AZ60A — Rev 2.0

304 Serial Peripheral Interface (SPI) MOTOROLA

19.10 Resetting the SPI

Any system reset completely resets the SPI. Partial reset occurs

whenever the SPI enable bit (SPE) is low. Whenever SPE is low, the

following occurs:

• The SPTE flag is set.

• Any transmission currently in progress is aborted.

• The shift register is cleared.

• The SPI state counter is cleared, making it ready for a new

complete transmission.

• All the SPI port logic is defaulted back to being general-purpose

I/O.

The following additional items are reset only by a system reset:

• All control bits in the SPCR register

• All control bits in the SPSCR register (MODFEN, ERRIE, SPR1,

and SPR0)

• The status flags SPRF, OVRF, and MODF

By not resetting the control bits when SPE is low, the user can clear SPE

between transmissions without having to reset all control bits when SPE

is set back to high for the next transmission.

By not resetting the SPRF, OVRF, and MODF flags, the user can still

service these interrupts after the SPI has been disabled. The user can

disable the SPI by writing 0 to the SPE bit. The SPI also can be disabled

by a mode fault occurring in an SPI that was configured as a master with

the MODFEN bit set.

Serial Peripheral Interface (SPI)

Low-Power Modes

MC68HC908AZ60A — Rev 2.0 Technical Data

MOTOROLA Serial Peripheral Interface (SPI) 305

19.11 Low-Power Modes

The WAIT and STOP instructions put the MCU in low power-

consumption standby modes.

19.11.1 Wait Mode

The SPI module remains active after the execution of a WAIT instruction.

In wait mode, the SPI module registers are not accessible by the CPU.

Any enabled CPU interrupt request from the SPI module can bring the

MCU out of wait mode.

If SPI module functions are not required during wait mode, reduce power

consumption by disabling the SPI module before executing the WAIT

instruction.

To exit wait mode when an overflow condition occurs, enable the OVRF

bit to generate CPU interrupt requests by setting the error interrupt

enable bit (ERRIE). (See Interrupts on page 301).

19.11.2 Stop Mode

The SPI module is inactive after the execution of a STOP instruction.

The STOP instruction does not affect register conditions. SPI operation

resumes after the MCU exits stop mode. If stop mode is exited by reset,

any transfer in progress is aborted and the SPI is reset.

19.12 SPI During Break Interrupts

The system integration module (SIM) controls whether status bits in

other modules can be cleared during the break state. The BCFE bit in

the SIM break flag control register (SBFCR, $FE03) enables software to

clear status bits during the break state. (See SIM Break Flag Control

To allow software to clear status bits during a break interrupt, write a

logic 1 to the BCFE bit. If a status bit is cleared during the break state, it

remains cleared when the MCU exits the break state.

Serial Peripheral Interface (SPI)

Technical Data MC68HC908AZ60A — Rev 2.0

306 Serial Peripheral Interface (SPI) MOTOROLA

To protect status bits during the break state, write a logic 0 to the BCFE

bit. With BCFE at logic 0 (its default state), software can read and write

I/O registers during the break state without affecting status bits. Some

status bits have a two-step read/write clearing procedure. If software

does the first step on such a bit before the break, the bit cannot change

during the break state as long as BCFE is at logic 0. After the break,

doing the second step clears the status bit.

Since the SPTE bit cannot be cleared during a break with the BCFE bit

cleared, a write to the data register in break mode will not initiate a

transmission nor will this data be transferred into the shift register.

Therefore, a write to the SPDR in break mode with the BCFE bit cleared

has no effect.

19.13 I/O Signals

The SPI module has four I/O pins and shares three of them with a

parallel I/O port.

• MISO — Data received

• MOSI — Data transmitted

• SPSCK — Serial clock

•SS — Slave select

•V

— Clock ground

The SPI has limited inter-integrated circuit (I

C) capability (requiring

software support) as a master in a single-master environment. To

communicate with I

C peripherals, MOSI becomes an open-drain output

when the SPWOM bit in the SPI control register is set. In I

communication, the MOSI and MISO pins are connected to a

bidirectional pin from the I

C peripheral and through a pullup resistor

to V

Part #	8A/S6
Description	Incandescent S Light Lamp
Category	LAMP
Availability	In Stock
Qty	2

8A/S6

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