GS8662D20/38BD-550/500/450/400/350
GS8662D06/11BD-500/450/400/350
72Mb SigmaQuad-II+
TM
Burst of 4 SRAM
550 MHz–350 MHz
1.8 V V
DD
1.8 V or 1.5 V I/O
165-Bump BGA
Commercial Temp
Industrial Temp
Rev: 1.02c 8/2017 1/33 © 2011, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Features
• 2.5 Clock Latency
• Simultaneous Read and Write SigmaQuad™ Interface
• JEDEC-standard pinout and package
• Dual Double Data Rate interface
• Byte Write controls sampled at data-in time
• Burst of 4 Read and Write
• On-Die Termination (ODT) on Data (D), Byte Write (
BW),
and Clock (K,
K) intputs
• 1.8 V +100/–100 mV core power supply
• 1.5 V or 1.8 V HSTL Interface
• Pipelined read operation
• Fully coherent read and write pipelines
• ZQ pin for programmable output drive strength
• Data Valid Pin (QVLD) Supp
ort
• IEEE 1149.1 JTAG-compliant Boundary Scan
• 165-bump, 13 mm x 15 mm, 1 mm bump pitch BGA package
• RoHS-compliant 165-bump BGA pa
ckage available
SigmaQuad-II™ Family Overview
The GS8662D06/11/20/38BD are built in compliance with
the SigmaQuad-II+ SRAM pinout standard for Separate I/O
synchronous SRAMs. They are 75,497,472-bit (72Mb)
SRAMs. The GS8662D06/11/20/38BD SigmaQuad SRAMs
are just one element in a family of low power, low voltage
HSTL I/O SRAMs designed to operate at the speeds needed to
implement economical high performance networking systems.
Clocking and Addressing Schemes
The GS8662D06/11/20/38BD SigmaQuad-II+ SRAMs are
synchronous devices. They employ two input register clock
inputs, K and
K. K and K are independent single-ended clock
inputs, not differential inputs to a single differential clock input
buffer.
Each internal read and write operat
ion in a SigmaQuad-II+ B4
RAM is four times wider than the device I/O bus. An input
data bus de-multiplexer is used to accumulate incoming data
before it is simultaneously written to the memory array. An
output data multiplexer is used to capture the data produced
from a single memory array read and then route it to the
appropriate output drivers as needed. Therefore the address
field of a SigmaQuad-II+ B4 RAM is always two address pins
less than the advertised index depth (e.g., the 8M x 8 has a 2M
addressable index).
Parameter Synopsis (x18/x36)
-550 -500 -450 -400 -350
tKHKH 1.81 ns 2.0 ns 2.2 ns 2.5 ns 2.86 ns
tKHQV 0.29ns 0.33 ns 0.37 ns 0.45 ns 0.45 ns
Parameter Synopsis (x8/x9)
-500 -450 -400 -350
tKHKH 2.0 ns 2.2 ns 2.5 ns 2.86 ns
tKHQV 0.33 ns 0.37ns 0.45 ns 0.45 ns
