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5962-9054301MXA

Part # 5962-9054301MXA
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Technical Document


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4-192
March 1997
82C37A
CMOS High Performance
Programmable DMA Controller
Features
Compatible with the NMOS 8237A
Four Independent Maskable Channels with Autoinitial-
ization Capability
Cascadable to any Number of Channels
High Speed Data Transfers:
- Up to 4MBytes/sec with 8MHz Clock
- Up to 6.25MBytes/sec with 12.5MHz Clock
Memory-to-Memory Transfers
Static CMOS Design Permits Low Power Operation
- ICCSB = 10µA Maximum
- ICCOP = 2mA/MHz Maximum
Fully TTL/CMOS Compatible
Internal Registers may be Read from Software
Description
The 82C37A is an enhanced version of the industry standard
8237A Direct Memory Access (DMA) controller, fabricated
using Intersil’s advanced 2 micron CMOS process. Pin
compatible with NMOS designs, the 82C37A offers
increased functionality, improved performance, and
dramatically reduced power consumption. The fully static
design permits gated clock operation for even further
reduction of power.
The 82C37A controller can improve system performance by
allowing external devices to transfer data directly to or from
system memory. Memory-to-memory transfer capability is
also provided, along with a memory block initialization fea-
ture. DMA requests may be generated by either hardware or
software, and each channel is independently programmable
with a variety of features for flexible operation.
The 82C37A is designed to be used with an external
address latch, such as the 82C82, to demultiplex the most
significant 8-bits of address. The 82C37A can be used with
industry standard microprocessors such as 80C286, 80286,
80C86, 80C88, 8086, 8088, 8085, Z80, NSC800, 80186 and
others. Multimode programmability allows the user to select
from three basic types of DMA services, and reconfiguration
under program control is possible even with the clock to the
controller stopped. Each channel has a full 64K address and
word count range, and may be programmed to autoinitialize
these registers following DMA termination (end of process).
Ordering Information
PART NUMBER
PACKAGE
TEMPERATURE
RANGE PKG. NO.5MHz 8MHz 12.5MHz
CP82C37A-5 CP82C37A CP82C37A-12 40 Ld PDIP 0
o
C to +70
o
C E40.6
IP82C37A-5 IP82C37A IP82C37A-12 -40
o
C to +85
o
C E40.6
CS82C37A-5 CS82C37A CS82C37A-12 44 Ld PLCC 0
o
C to +70
o
C N44.65
IS82C37A-5 IS82C37A IS82C37A-12 -40
o
C to +85
o
C N44.65
CD82C37A-5 CD82C37A CD82C37A-12 40 Ld CERDIP 0
o
C to +70
o
C F40.6
ID82C37A-5 ID82C37A ID82C37A-12 -40
o
C to +85
o
C F40.6
MD82C37A-5/B MD82C37A/B MD82C37A-12/B -55
o
C to +125
o
C F40.6
5962-9054301MQA 5962-9054302MQA 5962-9054303MQA SMD# F40.6
MR82C37A-5/B MR82C37A/B MR82C37A-12/B 44 Pad CLCC -55
o
C to +125
o
C J44.A
5962-9054301MXA 5962-9054302MXA 5962-9054303MXA SMD# J44.A
File Number 2967.1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207
| Copyright © Intersil Corporation 1999
4-193
82C37A
Block Diagram
Pinouts
82C37A (PDIP/CERDIP)
TOP VIEW
82C37A (CLCC/PLCC)
TOP VIEW
13
1
2
3
4
5
6
7
8
9
10
11
12
14
15
16
17
18
19
20
IOR
IOW
MEMR
MEMW
NC
READY
HLDA
ADSTB
AEN
HRQ
CS
CLK
RESET
DACK2
DACK3
DREQ3
DREQ2
DREQ1
DREQ0
(GND) VSS
28
40
39
38
37
36
35
34
33
32
31
30
29
27
26
25
24
23
22
21
A7
A6
A5
A4
EOP
A3
A2
A1
A0
VCC
DB0
DB1
DB2
DB3
DB4
DACK0
DACK1
DB5
DB6
DB7
14
13
12
11
10
9
8
7
17
16
15
25
30
35
39
38
37
36
33
34
32
31
29
4
6 3
1
40414243
44
2827262524232221201918
CS
DACK2
NC
NC
CLK
HRQ
NC
A3
A2
A1
A0
VCC
DB0
DB1
DB2
DB3
NC
DB4
READY
NC
A7
A6
A5
MEMW
A4
EOP
DACK3
DREQ3
DREQ2
DREQ1
DREQ0
GND
DB5
DACK1
DB7
DACK0
DB6
MEMR
ADSTB
AEN
IOW
RESET
HLDA
IOR
A4 - A7
EOP
RESET
CS
READY
CLK
AEN
ADSTB
MEMR
MEMW
IOR
IOW
TIMING
AND
CONTROL
DREQ0 -
HLDA
HRQ
DACK0 -
PRIORITY
ENCODER
AND
ROTATING
PRIORITY
LOGIC
DACK3
4
DREQ3
4
COMMAND
(8)
MASK
(4)
REQUEST
(4)
MODE
(4 x 6)
STATUS
(8)
TEMPORARY
(8)
INTERNAL DATA BUS
DECREMENTOR
COUNT REG (16)
TEMP WORD
INC/DECREMENTOR
REG (16)
TEMP ADDRESS
BUFFER
IO
16-BIT BUS
READ BUFFER
ADDRESS
BASE
(16)
WORD
BASE
COUNT
(16)
READ WRITE BUFFER
ADDRESS
CURRENT
(16)
WORD
CURRENT
COUNT
(16)
16-BIT BUS
BUFFER
WRITE
BUFFER
READ
A8 - A15
BUFFER
OUTPUT
CONTROL
COMMAND
D0 - D1
A0 - A3
BUFFER
IO
DB0 - DB7
4-194
82C37A
Pin Description
SYMBOL
PIN
NUMBER TYPE DESCRIPTION
V
CC
31 V
CC
: is the +5V power supply pin. A 0.1µF capacitor between pins 31 and 20 is recommended for
decoupling.
GND 20 Ground
CLK 12 I CLOCK INPUT: The Clock Input is used to generate the timing signals which control 82C37A
operations. This input may be driven from DC to 12.5MHz for the 82C37A-12, from DC to 8MHz for
the 82C37A, or from DC to 5MHz for the 82C37A-5. The Clock may be stopped in either state for
standby operation.
CS 11 I CHIP SELECT: Chip Select is an active low input used to enable the controller onto the data bus for
CPU communications.
RESET 13 I RESET: This is an active high input which clears the Command, Status, Request, and Temporary
registers, the First/Last Flip-Flop, and the mode register counter. The Mask register is set to ignore
requests. Following a Reset, the controller is in an idle cycle.
READY 6 I READY: This signal can be used to extend the memory read and write pulses from the 82C37A to
accommodate slow memories or I/O devices. READY must not make transitions during its specified
set-up and hold times. See Figure 12 for timing. READY is ignored in verify transfer mode.
HLDA 7 I HOLD ACKNOWLEDGE: The active high Hold Acknowledge from the CPU indicates that it has
relinquished control of the system busses. HLDA is a synchronous input and must not transition
during its specified set-up time. There is an implied hold time (HLDA inactive) of TCH from the rising
edge of CLK, during which time HLDA must not transition.
DREQ0-
DREQ3
16-19 I DMA REQUEST: The DMA Request (DREQ) lines are individual asynchronous channel request
inputs used by peripheral circuits to obtain DMA service. In Fixed Priority, DREQ0 has the highest
priority and DREQ3 has the lowest priority. A request is generated by activating the DREQ line of a
channel. DACK will acknowledge the recognition of a DREQ signal. Polarity of DREQ is
programmable. RESET initializes these lines to active high. DREQ must be maintained until the
corresponding DACK goes active. DREQ will not be recognized while the clock is stopped. Unused
DREQ inputs should be pulled High or Low (inactive) and the corresponding mask bit set.
DB0-DB7 21-23
26-30
I/O DATA BUS: The Data Bus lines are bidirectional three-state signals connected to the system data
bus. The outputs are enabled in the Program condition during the I/O Read to output the contents
of a register to the CPU. The outputs are disabled and the inputs are read during an I/O Write cycle
when the CPU is programming the 82C37A control registers. During DMA cycles, the most signifi-
cant 8-bits of the address are output onto the data bus to be strobed into an external latch by ADSTB.
In memory-to-memory operations, data from the memory enters the 82C37A on the data bus during
the read-from-memory transfer, then during the write-to-memory transfer, the data bus outputs write
the data into the new memory location.
IOR 1 I/O I/O READ: I/O Read is a bidirectional active low three-state line. In the Idle cycle, it is an input con-
trol signal used by the CPU to read the control registers. In the Active cycle, it is an output control
signal used by the 82C37A to access data from the peripheral during a DMA Write transfer.
IOW 2 I/O I/O WRITE: I/O Write is a bidirectional active low three-state line. In the Idle cycle, it is an input con-
trol signal used by the CPU to load information into the 82C37A. In the Active cycle, it is an output
control signal used by the 82C37A to load data to the peripheral during a DMA Read transfer.
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