National Semiconductor Corp 100336PC
Cross Number:
Item Description:
Counter/Shift Register Single4-Bit Binary UP/Down 24-Pin
Additional Information:
- Category: IC
- Is Military Spec.: No
- Availability: In Stock
- Qty Available: 10
| Qty | Price |
|---|---|
| 1 - 2 | $4.99633 |
| 3 - 4 | $3.97436 |
| 5 - 6 | $3.74725 |
| 7 - 8 | $3.48229 |
| 9 + | $3.10378 |
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Technical Document
DISCLAIMER: The information provided herein is solely for informational purposes. Customers must be aware of the suitability of this product for their application, and consider that variable factors such as Manufacturer, Product Category, Date Codes, Pictures and Descriptions may differ from available inventory.
© 2000 Fairchild Semiconductor Corporation DS010584 www.fairchildsemi.com
August 1989
Revised August 2000
100336 Low Power 4-Stage Counter/Shift Register
100336
Low Power 4-Stage Counter/Shift Register
General Description
The 100336 operates as either a modulo-16 up/down
counter or as a 4-bit bidirectional shift register. Three
Select (S
n
) inputs determine the mode of operation, as
shown in the Function Select table. Two Count Enable
(CEP
, CET) inputs are provided for ease of cascading in
multistage counters. One Count Enable (CET
) input also
doubles as a Serial Data (D
0
) input for shift-up operation.
For shift-down operation, D
3
is the Serial Data input. In
counting operations the Terminal Count (TC
) output goes
LOW when the counter reaches 15 in the count/up mode or
0 (zero) in the count/down mode. In the shift modes, the TC
output repeats the Q
3
output. The dual nature of this TC/Q
3
output and the D
0
/CET input means that one interconnec-
tion from one stage to the next higher stage serves as the
link for multistage counting or shift-up operation. The indi-
vidual Preset (P
n
) inputs are used to enter data in parallel
or to preset the counter in programmable counter applica-
tions. A HIGH signal on the Master Reset (MR) input over-
rides all other inputs and asynchronously clears the flip-
flops. In addition, a synchronous clear is provided, as well
as a complement function which synchronously inverts the
contents of the flip-flops. All inputs have 50 k
Ω pull-down
resistors.
Features
■ 40% power reduction of the 100136
■ 2000V ESD protection
■ Pin/function compatible with 100136
■ Voltage compensated operating range
= −4.2V to −5.7V
■ Available to industrial grade temperature range
Ordering Code:
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagrams
24-Pin DIP/SOIC 28-Pin PLCC
Logic Symbol
Order Number Package Number Package Description
100336SC M24B 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
100336PC N24E 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-010, 0.400 Wide
100336QC V28A 28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square
100336QI V28A 28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square
Industrial Temperature Range (
−40°C to +85°C)
www.fairchildsemi.com 2
100336
Function Select Table Pin Descriptions
Truth Table
Q
0
= LSB
1 = L if Q
0
–Q
3
= LLLL
H if Q
0
–Q
3
≠ LLLL
2 = L if Q
0
–Q
3
= HHHH
H if Q
0
–Q
3
≠ HHHH
H = HIGH Voltage Level
L = LOW Voltage Level
X = Don't Care
= LOW-to-HIGH Transition
Note 1: Before the clock, TC
is Q
3
After the clock, TC is Q
2
S
2
S
1
S
0
Function
L L L Parallel Load
L L H Complement
L H L Shift Left
L H H Shift Right
H L L Count Down
HLHClear
H H L Count Up
HHHHold
Pin Names Description
CP Clock Pulse Input
CEP
Count Enable Parallel Input (Active LOW)
D
0
/CET Serial Data Input/Count Enable
Trickle Input (Active LOW)
S
0
–S
2
Select Inputs
MR Master Reset Input
P
0
–P
3
Preset Inputs
D
3
Serial Data Input
TC
Terminal Count Output
Q
0
–Q
3
Data Outputs
Q
0
–Q
3
Complementary Data Outputs
Inputs Outputs
MR S
2
S
1
S
0
CEP D
0
/CET D
3
CP Q
3
Q
2
Q
1
Q
0
TC Mode
L LLL X X X
P
3
P
2
P
1
P
0
L Preset (Parallel Load)
LLLHX X X
Q
3
Q
2
Q
1
Q
0
LInvert
LLHL X X X
D
3
Q
3
Q
2
Q
1
D
3
Shift to LSB
LLHHX X X
Q
2
Q
1
Q
0
D
0
Q
3
(Note 1) Shift to MSB
LHLL L L X
(Q
0–3
) minus 1 1 Count Down
LHLL H L XXQ
3
Q
2
Q
1
Q
0
1 Count Down with CEP not active
LHLL X H XXQ
3
Q
2
Q
1
Q
0
H Count Down with CET not active
LHLH X X X
LLLL H Clear
LHHL L L X
(Q
0–3
) plus 1 2 Count Up
LHHL H L XXQ
3
Q
2
Q
1
Q
0
2 Count Up with CEP not active
LHHL X H XXQ
3
Q
2
Q
1
Q
0
H Count Up with CET not active
L HHH X X X XQ
3
Q
2
Q
1
Q
0
HHold
HLLL X X XXLLLL L
HLLH X X XXLLLL L
HLHL X X XXLLLL L
H L H H X X X X L L L L L Asynchronous
H H L L X L X X L L L L L Master Reset
HHLL X H XXLLLL H
HHLH X X XXLLLL H
HHHL X X XXLLLL H
H HHH X X X X L L L L H
3 www.fairchildsemi.com
100336
Logic Diagram
