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5962-8957701XA

Part # 5962-8957701XA
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Date Code: 9442
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Technical Document


DISCLAIMER: The information provided herein is solely for informational purposes. Customers must be aware of the suitability of this product for their application, and consider that variable factors such as Manufacturer, Product Category, Date Codes, Pictures and Descriptions may differ from available inventory.

BCRTM-1
UT1553 BCRTM
FEATURES
p Comprehensive MIL-STD-1553 dual-redundant Bus
Controller (BC) and Remote Terminal (RT) and
Monitor (M) functions
p MIL-STD-1773 compatible
p Multiple message processing capability in BC
p Time tagging and message logging in RT and M modes
p Automatic polling and intermessage delay in
BC mode
p Programmable interrupt scheme and internally
generated interrupt history list
p Register-oriented architecture to enhance
programmability
p DMA memory interface with 64K addressability
p Internal self-test
p Radiation-hardened option available for 84-lead
flatpack package only
p Remote terminal operations in ASD/ENASD-certified
(SEAFAC)
p Available in 84-pin pingrid array, 84-lead flatpack, 84-
lead leadless chip-carrier
p Standard Microcircuit Drawing 5962-89577 available
- QML Q and V compliant
16
16
16
CONTROL
DMA/CPU
MESSAGE
RT/MONITOR
MESSAGE
BC PROTOCOL
HANDLER
INTERRUPT
CONVER-
PARALLEL
SERIAL-TO-
CONVER-
TO-SERIAL
PARALLEL-
MODULE
DECODER
ENCODER/
CHANNEL
DUAL
BUS
TRANSFER
LOGIC
ADDRESS
16
TIMEOUT
TIMERON
CLOCK &
RESET
12MHz
MASTER
RESET
GENERATOR
ADDRESS
16
1553
HIGH-PRIORITY
RT ADDRESS
STANDARD INTERRUPT
HIGH-PRIORITY
INTERRUPT LOG
CURRENT COMMAND
BUILT-IN-TEST WORD
POLLING COMPARE
CURRENT BC (or M) BLOCK/
STATUS
CONTROL
REGISTERS
LIST POINTER
DATA
16
BUILT-
IN-
TEST
16
16
MONITOR ADDRESS
INTERRUPT STATUS
INTERRUPT ENABLE
SION
SION
PROTOCOL &
HANDLER
&
HANDLER
DATA
CHANNEL
B
1553
DATA
CHANNEL
A
LOGIC
HIGH-PRIORITY
STD PRIORITY LEVEL
STD PRIORITY PULSE
DMA ARBITRATION
REGISTER CONTROL
DUAL-PORT MEMORY CONTROL
RT DESCRIPTOR SPACE
ENABLE
BUILT-IN-TEST
START COMMAND
RESET COMMAND
CONTROL
MONITOR ADDRESS
SELECT (0-15)
MONITOR ADDRESS
Figure 1. BCRTM Block Diagram
SELECT (16-31)
RT TIMER
RESET COMMAND
BCRTM-2
Table of Contents
1.0 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.1 Features - Remote Terminal (RT) Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
1.2 Features - Bus Controller (BC) Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
1.3 Features - Monitor (M) Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
2.0 PIN IDENTIFICATION AND DESCRIPTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3.0 INTERNAL REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.0 SYSTEM OVERVIEW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
5.0 SYSTEM INTERFACE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
5.1 DMA Transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
5.2 Hardware Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
5.3 CPU Interconnection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
5.4 RAM Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
5.6 Transmitter/Receiver Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
6.0 REMOTE TERMINAL ARCHITECTURE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
6.1 RT Functional Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
6.1.1 RT Subaddress Descriptor Definitions. . . . . . . . . . . . . . . . . . . . . . . . . .24
6.1.2 Message Status Word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
6.1.3 Mode Code Descriptor Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
6.2 RT Error Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
6.3 RT Operational Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
7.0 BUS CONTROLLER ARCHITECTURE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
7.1 BC Functional Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
7.2 Polling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
7.3 BC Error Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
7.4 BC Operational Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
7.5 BC Operational Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
8.0 MONITOR ARCHITECTURE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
8.1 Monitor Functional Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
8.2 Monitor Error Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
8.3 Monitor Operational Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
9.0 EXCEPTION HANDLING AND INTERRUPT LOGGING . . . . . . . . . . . . . . . . . . . . . . . . 36
10.0 MAXIMUM AND RECOMMENDED OPERATING CONDITIONS . . . . . . . . . . . . . . . . 40
11.0 DC ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
12.0 AC ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
13.0 PACKAGE OUTLINE DRAWINGS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
BCRTM-3
1.0 INTRODUCTION
The monolithic CMOS UT1553 BCRTM provides the
system designer with an intelligent solution to
MIL-STD-1553B multiplexed serial data bus design
problems. The UT1553B BCRTM is a single-chip device
that implements all three of defined MIL-STD-1553B
functions - Bus Controller, Remote Terminal, and Monitor.
Designed to reduce host CPU overhead, the BCRTM’s
powerful state machines automatically execute message
transfers, provide interrupts, and generate status
information. Multiple registers offer many programmable
functions as well as extensive information for host use. In
the BC mode, the BCRTM uses a linked-list message
scheme to provide the host with message chaining
capability. The BCRTM enhances memory use by
supporting variable-size, relocatable data blocks. In the RT
mode, the BCRTM implements time-tagging and message
history functions. It also supports multiple (up to 128)
message buffering and variable length messages to any
subaddress.In the Monitor (M) mode, the BCRTM’s
powerful linked list command block structure allows it to
process a series of monitored 1553 messages without the
intervention of the host. The BCRTM can store as much bus
traffic as can be contained in its 64K memory space. In
addition, the host has the capability of instructing the
BCRTM to monitor and store data for only selected remote
terminals.
The UT1553 BCRTM is an intelligent, versatile, and easy
to implement device -- a powerful asset to system designers.
1.1 Features - Remote Terminal (RT) Mode
Indexing
The BCRTM is programmable to index or buffer messages
on a subaddress-by-subaddress basis. The BCRTM, which
can index as many as 128 messages, can also assert an
interrupt when either the selected number of messages is
reached or every time a specified subaddress is accessed.
Variable Space Allocation
The BCRTM can use as little or as much memory (up to
64K) as needed.
Selectable Data Storage
Address programmability within the BCRTM provides
flexible data placement and convenient access.
Sequential Data Storage
The BCRTM stores/retrieves, by subaddress, all messages
in the order in which they are transacted.
Sequential Message Status Information
The BCRTM provides message validity, time-tag, and
word-count information, and stores it sequentially in a
separate, cross-referenced list.
Illegalizing Mode Codes and Subaddresses
The host can declare mode codes and subaddresses illegal
by setting the appropriate bit(s) in memory.
Programmable Interrupt Selection
The host CPU can select various events to cause an interrupt
with provision for high and standard priority interrupts.
Interrupt History List
The BCRTM provides an Interrupt History List that records,
in the order of occurrence, the events that caused the
interrupts. The list length is programmable.
1.2 Features - Bus Controller (BC) Mode
Multiple Message Processing
The BCRTM autonomously processes any number of
messages or lists of messages that may be stored in a 64K
memory space.
Automatic Intermessage Delay
When programmed by the host, the BCRTM can delay a
host-specified time before executing the next message in
sequence.
Automatic Polling
When polling, the BCRTM interrogates the remote
terminals and then compares their status word responses to
the contents of the Polling Compare Register. The BCRTM
can interrupt the host CPU if an erroneous remote terminal
status word response occurs.
Automatic Retry
The BCRTM can automatically retry a message on busy,
message error, and/or response time-out conditions. The
BCRTM can retry up to four times on the same or on the
alternate bus.
Programmable Interrupt Selection
The host CPU can select various events to cause an interrupt
with provision for high and standard priority interrupts.
Interrupt History List
The BCRTM provides an Interrupt History List that records,
in the order of occurrence, the events that caused the
interrupts. The list length is programmable.
Variable Space Allocation
The BCRTM uses as little or as much memory (up to 64K)
as needed.
Selectable Data Storage
Address programmability within the BCRTM provides
flexible data placement and convenient access.
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