4-327
82C87H
Functional Diagram
Gated Inputs
During normal system operation of a latch, signals on the
bus at the device inputs will become high impedance or
make transitions unrelated to the operation of the latch.
These unrelated input transitions switch the input circuitry
and typically cause an increase in power dissipation in
CMOS devices by creating a low resistance path between
V
CC
and GND when the signal is at or near the input switch-
ing threshold. Additionally, if the driving signal becomes high
impedance (“float” condition), it could create an indetermi-
nate logic state at the inputs and cause a disruption in
device operation.
The Intersil 82C8X series of bus drivers eliminates these
conditions by turning off data inputs when data is latched
(STB = logic zero for the 82C82/83H) and when the device is
disabled (
OE = logic one for the 82C87H/87H). These gated
inputs disconnect the input circuitry from the V
CC
and
ground power supply pins by turning off the upper P-Chan-
nel and lower N-Channel (See Figures 1 and 2). No current
flow from V
CC
to GND occurs during input transitions and
invalid logic states from floating inputs are not transmitted.
The next stage is held to a valid logic level internal to the
device.
D.C. input voltage levels can also cause an increase in ICC if
these input levels approach the minimum V
IH
or maximum
V
IL
conditions. This is due to the operation of the input cir-
cuitry in its linear operating region (partially conducting
state). The 82C8X series gated inputs mean that this condi-
tion will occur only during the time the device is in the trans-
parent mode (STB = logic one). ICC remains below the
maximum ICC standby specification of 10µA during the time
inputs are disabled, thereby greatly reducing the average
power dissipation of the 82C8X series devices.
Decoupling Capacitors
The transient current required to charge and discharge the
300pF load capacitance specified in the 82C86H/87H data
sheet is determined by:
Assuming that all outputs change state at the same time and
that dv/dt is constant;
where tR = 20ns, V
CC
= 5.0V, C
L
= 300pF on each eight out-
puts.
This current spike may cause a large negative voltage spike on
V
CC
which could cause improper operation of the device. To fil-
ter out this noise, it is recommended that a 0.1µF ceramic disc
capacitor be placed between V
CC
and GND at each device,
with placement being as near to the device as possible.
T
B7
B6
B5
B4
B3
B2
B1
B0
A0
A1
A2
A3
A4
A5
A6
A7
OE
IC
L
dv dt⁄()=
(EQ. 4)
IC
L
VCC 80%×()
tR tF⁄
-------------------------------------
=
(EQ. 5)
I 80 300 10
12–
××()5.0V 0.8×()20 10
9–
×()⁄×=
480mA=
(EQ. 6)
STB
DATA IN
V
CC
P
N
V
CC
INTERNAL
DATA
P
P
N
N
FIGURE 3. 82C82/83H
DATA IN
INTERNAL
DATA
V
CC
V
CC
N
N
P
P
P
N
OE
FIGURE 4. 82C86H/87H GATED INPUTS
82C87H
