Name: 5962-85016013A
SKU: 5962-85016013A
Price: 73.62577 USD
Availability: InStock

4-1

March 1997

82C59A

CMOS Priority Interrupt Controller

Features

• 12.5MHz, 8MHz and 5MHz Versions Available

- 12.5MHz Operation. . . . . . . . . . . . . . . . . . .82C59A-12

- 8MHz Operation . . . . . . . . . . . . . . . . . . . . . . . 82C59A

- 5MHz Operation . . . . . . . . . . . . . . . . . . . . . .82C59A-5

• High Speed, “No Wait-State” Operation with 12.5MHz

80C286 and 8MHz 80C86/88

• Pin Compatible with NMOS 8259A

• 80C86/88/286 and 8080/85/86/88/286 Compatible

• Eight-Level Priority Controller, Expandable to

64 Levels

• Programmable Interrupt Modes

• Individual Request Mask Capability

• Fully Static Design

• Fully TTL Compatible

• Low Power Operation

- ICCSB . . . . . . . . . . . . . . . . . . . . . . . . . 10µA Maximum

- ICCOP . . . . . . . . . . . . . . . . . . . . . 1mA/MHz Maximum

• Single 5V Power Supply

• Operating Temperature Ranges

- C82C59A . . . . . . . . . . . . . . . . . . . . . . . . .0

C to +70

- I82C59A . . . . . . . . . . . . . . . . . . . . . . . . -40

C to +85

- M82C59A . . . . . . . . . . . . . . . . . . . . . . -55

C to +125

Description

The Intersil 82C59A is a high performance CMOS Priority

Interrupt Controller manufactured using an advanced 2µm

CMOS process. The 82C59A is designed to relieve the sys-

tem CPU from the task of polling in a multilevel

priority system. The high speed and industry standard

conﬁguration of the 82C59A make it compatible with micro-

processors such as 80C286, 80286, 80C86/88, 8086/88,

8080/85 and NSC800.

The 82C59A can handle up to eight vectored priority inter-

rupting sources and is cascadable to 64 without additional

circuitry. Individual interrupting sources can be masked or

prioritized to allow custom system conﬁguration. Two modes

of operation make the 82C59A compatible with both 8080/85

and 80C86/88/286 formats.

Static CMOS circuit design ensures low operating power.

The Intersil advanced CMOS process results in performance

equal to or greater than existing equivalent products at a

fraction of the power.

Ordering Information

PART NUMBER

PACKAGE

TEMPERATURE

RANGE PKG. NO.5MHz 8MHz 12.5MHz

CP82C59A-5 CP82C59A CP82C59A-12 28 Ld PDIP 0

C to +70

C E28.6

IP82C59A-5 IP82C59A IP82C59A-12 -40

C to +85

C E28.6

CS82C59A-5 CS82C59A CS82C59A-12 28 Ld PLCC 0

C to +70

C N28.45

IS82C59A-5 IS82C59A IS82C59A-12 -40

C to +85

C N28.45

CD82C59A-5 CD82C59A CD82C59A-12 CERDIP 0

C to +70

C F28.6

ID82C59A-5 ID82C59A ID82C59A-12 -40

C to +85

C F28.6

MD82C59A-5/B MD82C59A/B MD82C59A-12/B -55

C to +125

C F28.6

5962-8501601YA 5962-8501602YA - SMD# F28.6

MR82C59A-5/B MR82C59A/B MR82C59A-12/B 28 Pad CLCC -55

C to +125

C J28.A

5962-85016013A 5962-85016023A - SMD# J28.A

CM82C59A-5 CM82C59A CM82C59A-12 28 Ld SOIC 0

C to +70

C M28.3

File Number 2784.2

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

http://www.intersil.com or 407-727-9207

4-2

Functional Diagram

Pinouts

82C59A (PDIP, CERDIP, SOIC)

TOP VIEW

82C59A (PLCC, CLCC)

TOP VIEW

PIN DESCRIPTION

D7 - D0 Data Bus (Bidirectional)

RD Read Input

WR Write Input

A0 Command Select Address

CS Chip Select

CAS 2 - CAS 0 Cascade Lines

SP/EN Slave Program Input Enable

INT Interrupt Output

INTA Interrupt Acknowledge Input

IR0 - IR7 Interrupt Request Inputs

CAS 0

CAS 1

GND

INTA

IR7

IR6

IR5

IR3

IR1

IR0

INT

SP/EN

CAS 2

IR4

IR2

3 2

14 15 16 17 18

28 27 26

INTA

IR7

IR6

IR5

IR4

IR3

IR2

IR1

CAS 0

IR0

CAS 1

GND

CAS 2

SP/ EN

INT

PRIORITY

RESOLVER

IR0

IR1

IR2

IR3

IR4

IR5

IR6

IR7

INTERRUPT

REQUEST

REG

(IRR)

INTERRUPT MASK REG

(IMR)

CONTROL LOGIC

INTERNAL BUS

INT

DATA

BUS

BUFFER

CASCADE

BUFFER

COMPARATOR

CAS 0

CAS 1

CAS 2

READ/

WRITE

LOGIC

SP/EN

INTA

IN -

SERVICE

REG

(ISR)

-D

FIGURE 1.

82C59A

4-3

Functional Description

Interrupts in Microcomputer Systems

Microcomputer system design requires that I/O devices such

as keyboards, displays, sensors and other components

receive servicing in an efﬁcient manner so that large

amounts of the total system tasks can be assumed by the

microcomputer with little or no effect on throughput.

The most common method of servicing such devices is the

Polled approach. This is where the processor must test each

device in sequence and in effect “ask” each one if it needs

servicing. It is easy to see that a large portion of the main

program is looping through this continuous polling cycle and

that such a method would have a serious, detrimental effect

on system throughput, thus, limiting the tasks that could be

assumed by the microcomputer and reducing the cost effec-

tiveness of using such devices.

Pin Description

SYMBOL

NUMBER TYPE DESCRIPTION

28 I V

: The +5V power supply pin. A 0.1µF capacitor between pins 28 and 14 is recommended for

decoupling.

GND 14 I GROUND

CS 1 I CHIP SELECT: A low on this pin enables RD and WR communications between the CPU and the

82C59A. INTA functions are independent of CS.

WR 2 I WRITE: A low on this pin when CS is low enables the 82C59A to accept command words from

the CPU.

RD 3 I READ: A low on this pin when CS is low enables the 82C59A to release status onto the data bus

for the CPU.

D7 - D0 4 - 11 I/O BIDIRECTIONAL DATA BUS: Control, status, and interrupt-vector information is transferred via

this bus.

CAS0 - CAS2 12, 13, 15 I/O CASCADE LINES: The CAS lines form a private 82C59A bus to control a multiple 82C59A struc-

ture. These pins are outputs for a master 82C59A and inputs for a slave 82C59A.

SP/EN 16 I/O SLAVE PROGRAM/ENABLE BUFFER: This is a dual function pin. When in the Buffered Mode it

can be used as an output to control buffer transceivers (EN). When not in the Buffered Mode it is

used as an input to designate a master (SP = 1) or slave (SP = 0).

INT 17 O INTERRUPT: This pin goes high whenever a valid interrupt request is asserted. It is used to inter-

rupt the CPU, thus, it is connected to the CPU's interrupt pin.

IR0 - IR7 18 - 25 I INTERRUPT REQUESTS: Asynchronous inputs. An interrupt request is executed by raising an

IR input (low to high), and holding it high until it is acknowledged (Edge Triggered Mode), or just

by a high level on an IR input (Level Triggered Mode). Internal pull-up resistors are implemented

on IR0 - 7.

INTA 26 I INTERRUPT ACKNOWLEDGE: This pin is used to enable 82C59A interrupt-vector data onto the

data bus by a sequence of interrupt acknowledge pulses issued by the CPU.

A0 27 I ADDRESS LINE: This pin acts in conjunction with the CS, WR, and RD pins. It is used by the

82C59A to decipher various Command Words the CPU writes and status the CPU wishes to read.

It is typically connected to the CPU A0 address line (A1 for 80C86/88/286).

ROM

I/O (N)

I/O (2)

I/O (1)RAM

CPU

CPU - DRIVEN

MULTIPLEXER

FIGURE 2. POLLED METHOD

82C59A

Part #	5962-85016013A
Description	INTERRUPT CONTROLLER
Category	IC
Availability	In Stock
Qty	9

Qty	Price
1 - 1	$73.62577
2 - 3	$58.56596
4 - 5	$55.21933
6 - 7	$51.31493
8 +	$45.73722

Manufacturer	Available	Qty
Harris Corporation Date Code: 9511	Freelance Stock: 6 Ships Immediately
INTERSIL Date Code: 0250	Freelance Stock: 3 Ships Immediately

5962-85016013A

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